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mc81f4 204 october 19, 2009 ver. 1.35 1 abov semiconductor 8 - bit single - chip microcontrollers mc8 1 f 4 204 mc81f4204 r /m/v/d/b users manual (ver. 1. 3 5 )
mc81f4 204 2 october 19, 2009 ver. 1.35 version 1.35 published by fae team ?
mc81f4 204 october 19, 2009 ver. 1.35 3 revision history version 1.3 5 ( o c t o b e r 1 9 , 2009 ) this book a d d a n o t e a b o u t s c k p o r t a t r 0 c o n m r e g i s t e r d e s c r i p t i o n . change eva.board picture. (the board ? s color is changed from blue to green) version 1.34 ( september 30, 2009 ) correct the duty equation of pmw0/1. add more tools at 1.3 development tools . version 1.33 ( september 18, 2009 ) a dd more descriptions at pwm function descriptions. version 1.3 2 ( september 4 , 2009 ) remove rising /falling time at lvr electrical characteristics. change ? 1.83v ? to por level in por description. add por level at dc characteristics . add rom option read timing information. add typical characteristics . version 1.22 ( august 12, 2009 ) add 16tssop at 16pin pin assignment page. re move fxt(sub - clock source) at block diagrams and register descriptions of t0/1/2 and buzzer . version 1.21 ( july 7, 2009 ) 25.3 hardware conditions to enter the isp mode is updated. note s of r35 port control register s are updated. r3conh, r3conl register ? s address are corrected at table 9 - 4 control register 4/4 r1 port pull - up enable register table is corrected. version 1. 2 ( june 29 , 2009 ) remove ? wdt ? at stop release description . ? wdt ? is not a release source of stop mode. change fxin to fbuz at buzzer f requency calculation in buzzer chapter. version 1.1 (june 17, 2009 ) add rom writing endurance at features. remove 16 bit mode at timer0. version 1.0 ( june 15 , 2009 ) remove preliminary . some errata are fixed. add buzzer frequency table .
mc81f4 204 4 october 19, 2009 ver. 1.35 version 0 . 81 preliminary (april 28, 2009 ) delete a note1 at ? 20.5 recommended circuit ? . version 0 . 8 preliminary ( april 16 , 2009 ) add a sub - chapter ? changing the stabilizing time ? at the chapter ? power down operation ? . add a note for r33/r34 ports after r3conh description. one of bit ? s clock source ? 2048 ? is changed to ? 1024 ? . version 0 . 7 preliminary (april 7, 2009 ) descripti on of sio procedure is updated. description of isp chapter is updated. version 0 . 6 preliminary (april 1 , 2009 ) c hapter ? 7.electical charictoristics ? is updated. version 0 . 5 preliminary (march 5, 2009 ) the sclk pin for isp is moved to r11 port. note for adc recommended circuit is changed. version 0 . 4 preliminary (february 12, 2009 ) correct 16 sop package diagram. update the chapter ? 6. port structure ? . update the chapter ? 7. electrical characteristics ? . update the chapter ? 25. in system programming ? . version 0 . 3 preliminary ( december 19 , 2008) block diagrams of timer 2/3 and pwm are corrected. version 0 . 2 preliminary ( november 17 , 2008) some errata are corrected. version 0 . 1 preliminary ( november 12 , 2008) change some bit and symbol names about int errupts. version 0 .0 preliminary ( october 31 , 2008)
mc81f4 204 october 19, 2009 ver. 1.35 5 table of contents revision history ................................ ................................ ................................ .............................. 3 table of contents ................................ ................................ ................................ .......................... 5 1. overview ................................ ................................ ................................ ................................ ......... 8 1.1 description ................................ ................................ ................................ ................................ .... 8 1.2 features ................................ ................................ ................................ ................................ ........ 8 1.3 development tools ................................ ................................ ................................ ....................... 9 1.4 ordering information ................................ ................................ ................................ ................... 10 2. block diagram ................................ ................................ ................................ ............................ 11 3. pin assignment ................................ ................................ ................................ ........................... 12 3.1 20 pin - p dip/sop ................................ ................................ ................................ ....................... 12 3.2 16 pin - pdi p/sop /tssop ................................ ................................ ................................ .......... 12 3.3 summary ................................ ................................ ................................ ................................ ..... 13 4. package diagram ................................ ................................ ................................ ....................... 14 4.1 20 pdip - mc81f4204b ................................ ................................ ................................ .............. 14 4.2 20 sop - mc81f4204d ................................ ................................ ................................ .............. 14 4.3 16 pdip - mc81f4204v ................................ ................................ ................................ ............. 15 4.4 16 sop - mc81f4204m ................................ ................................ ................................ ............. 15 4.5 16 tssop - MC81F4204R ................................ ................................ ................................ ......... 16 5. pin description ................................ ................................ ................................ ........................... 17 6. port structure ................................ ................................ ................................ ......................... 20 7. electrical characteristics ................................ ................................ ................................ . 24 7.1 absolute maximum ra tings ................................ ................................ ................................ ........ 24 7.2 recommended operating conditions ................................ ................................ ........................ 24 7.3 a/d converter characteristics ................................ ................................ ................................ .... 25 7.4 dc electrical characteristics ................................ ................................ ................................ ...... 26 7.5 dc electrical characteristics (continued) ................................ ................................ .................. 27 7.6 input/output capacitance ................................ ................................ ................................ ........... 27 7.7 serial i/o characteristics ................................ ................................ ................................ ............ 28 7.8 data retention voltage in stop mode ................................ ................................ ........................ 30 7.9 lvr (low voltage reset) electrical characteristics ................................ ................................ .. 31 7.10 main clock oscillator characteristics ................................ ................................ ........................ 32 7.11 external rc oscillation characteristics ................................ ................................ .................... 33 7.12 internal rc oscillation characteristics ................................ ................................ ..................... 34 7.13 main oscillation stabilization time ................................ ................................ ........................... 34 7.14 operating voltage range ................................ ................................ ................................ ......... 35 7.15 typical characteristics ................................ ................................ ................................ .............. 36 8. rom option ................................ ................................ ................................ ................................ ... 40 8.1 rom option ................................ ................................ ................................ ................................ . 40 8.2 read timing ................................ ................................ ................................ ................................ 41 9 . memory organization ................................ ................................ ................................ .............. 42 9.1 registers ................................ ................................ ................................ ................................ ..... 42 9.2 program memory ................................ ................................ ................................ ........................ 46 9.3 data memory ................................ ................................ ................................ .............................. 49 9.4 user memory ................................ ................................ ................................ .............................. 49 9.5 stack area ................................ ................................ ................................ ................................ .. 50
mc81f4 204 6 october 19, 2009 ver. 1.35 9.6 control registers ( sfr ) ................................ ................................ ................................ ........... 50 9.7 addressing modes ................................ ................................ ................................ ...................... 55 10. i/o ports ................................ ................................ ................................ ................................ ...... 62 10.1 r0 port registers ................................ ................................ ................................ ..................... 63 10.2 r1 port registers ................................ ................................ ................................ ..................... 67 10.3 r3 port registers ................................ ................................ ................................ ..................... 71 11. interrutp controller ................................ ................................ ................................ .......... 73 11.1 registers ................................ ................................ ................................ ................................ ... 74 11.2 interrupt sequence ................................ ................................ ................................ ................... 76 11.3 brk interrupt ................................ ................................ ................................ ............................ 79 11.4 shared interrupt vector ................................ ................................ ................................ ............ 79 11.5 multi interrupt ................................ ................................ ................................ ............................ 80 11.6 interrupt vector & priority table ................................ ................................ ............................... 81 12. external interrupts ................................ ................................ ................................ ............. 82 12.1 registers ................................ ................................ ................................ ................................ ... 82 12.2 procedure ................................ ................................ ................................ ................................ . 85 13. oscillation circuits ................................ ................................ ................................ .............. 86 13.1 main oscillation circuits ................................ ................................ ................................ ........... 86 13.2 pcb layout ................................ ................................ ................................ ............................... 87 14. basic interval timer ................................ ................................ ................................ ............... 88 14.1 registers ................................ ................................ ................................ ................................ ... 89 15. watch dog timer ................................ ................................ ................................ ...................... 90 15.1 registers ................................ ................................ ................................ ................................ ... 91 1 6. timer 0/1 ................................ ................................ ................................ ................................ ......... 92 16.1 registers ................................ ................................ ................................ ................................ ... 92 16.2 timer 0 8 - b it mode ................................ ................................ ................................ ................... 96 16.3 timer 1 8 - bit mode ................................ ................................ ................................ ................... 98 17. timer 2 ................................ ................................ ................................ ................................ .......... 100 17.1 registers ................................ ................................ ................................ ................................ . 100 17.2 timer 2 8 - bit mode ................................ ................................ ................................ ................. 102 18. high speed pwm ................................ ................................ ................................ .......................... 104 18.1 registers ................................ ................................ ................................ ................................ . 106 19. buzzer ................................ ................................ ................................ ................................ ........ 108 19.1 registers ................................ ................................ ................................ ................................ . 109 19.2 frequency table ................................ ................................ ................................ ...................... 110 20. 12 - bit adc ................................ ................................ ................................ ................................ ... 111 20.1 registers ................................ ................................ ................................ ................................ . 112 20.2 procedure ................................ ................................ ................................ ............................... 113 20.3 c onversion timing ................................ ................................ ................................ .................. 113 20.4 i nternal reference v oltage l evels ................................ ................................ ......................... 114 20.5 recommended circuit ................................ ................................ ................................ ............ 114 21. serial i/o interface ................................ ................................ ................................ .............. 115 21.1 registers ................................ ................................ ................................ ................................ . 116 21.2 procedure ................................ ................................ ................................ ............................... 117 22. reset ................................ ................................ ................................ ................................ .......... 118 22.1 reset process ................................ ................................ ................................ ........................ 118 22.2 reset sources ................................ ................................ ................................ ........................ 119 22.3 external reset ................................ ................................ ................................ ........................ 119
mc81f4 204 october 19, 2009 ver. 1.35 7 22.4 watch dog timer reset ................................ ................................ ................................ ......... 120 22.5 power on reset ................................ ................................ ................................ ..................... 121 22.6 low voltage reset ................................ ................................ ................................ .................. 121 23. power down operation ................................ ................................ ................................ ...... 122 23.1 sleep mode ................................ ................................ ................................ ............................. 122 23.2 stop mode ................................ ................................ ................................ ............................... 124 23.3 sleep vs stop ................................ ................................ ................................ .......................... 127 23.4 changing the stabilizing time ................................ ................................ ................................ .. 128 23.5 minimizing current consumption ................................ ................................ ........................... 128 24. emulator ................................ ................................ ................................ ................................ .. 130 25. in system programming ................................ ................................ ................................ ...... 133 25.1 getting started ................................ ................................ ................................ ........................ 133 25.2 basic isp s/w information ................................ ................................ ................................ ..... 134 25.3 hardware condition s to enter the isp mode ................................ ................................ .......... 136 25.4 entering isp mode at power on time ................................ ................................ ...................... 137 25.5 usb - sio - isp board ................................ ................................ ................................ ............... 138 26. instruction set ................................ ................................ ................................ ...................... 139 26.1 terminology list ................................ ................................ ................................ ..................... 139 26.2 instruction map ................................ ................................ ................................ ....................... 140 26.3 instruction set ................................ ................................ ................................ ......................... 141
mc81f4 204 8 october 19, 2009 ver. 1.35 mc 81 f 4 204 8 bit mcu with 1 2 - bit a/d converter 1. overview 1.1 description mc81f 4 204 is a cm os 8 bit mcu which provides a 4 k bytes flash - rom and 192 bytes ram. it has following major features, 12 bit adc : it has 1 0 ch a/d converter which can be used to measure minute electronic voltage and currents. 810 core : same with abov ? s 800 core but twice faster. 800 core use a divided system clock but 810 c ore use a system clock directly 1.2 features rom (flash) : 4k byte s (endurance: 100 cycle) sram : 192 bytes minimum instruction execution time 166 n s ec at 12 mhz (nop instruction) 1 2 - bit a/d converter : 10 ch general purpose i/o (gpio) 20 - pin pkg : 18 16 - pin pkg : 14 timer/counter 8bit x 3ch sio : 1ch pwm 8bit x 2ch 10bit x 2ch (high speed pwm) basic interval timer (bit) : 8bit x 1ch one watchdog timer (wdt) : 8bit x 1ch buzzer : 1ch 244 ~ 250khz @8mhz p ower on reset (por) low voltage reset (lvr) 4 level detector (2.4/2.7/3.0/4.0v) i nterrupt sources : 21ch ext ernal interrupt : 12 ch timer : 8 ch sio : 1 ch power down mode stop mode sleep mode operating voltage & frequency 2. 2 v C 5.5v (at 1.0 C 4.2 mhz) 2.7 v C 5.5v (at 1.0 C 8 .0 mhz) 4. 0 v C 5.5v (at 1.0 C 12 .0 mhz) operating temperature - 40c ~ 85c oscillator type crystal , ceramic , rc for main clock internal oscillator ( 8mhz/ 4mhz/2mhz /1mhz ) package 2 0p dip, 2 0 sop 16p dip, 16sop, 16tssop available pb free package
mc81f4 204 october 19, 2009 ver. 1.35 9 1.3 development tools the mc8 1 f 4 204 is supported by a full - featured macro assembler, c - compiler, an in - circuit emulator choice - dr. tm , falsh programmers and isp tools . there are two different type of programmers such as si ngle type and gang type. for mo r e detail, macro assembler operates under the ms - windows 95 and up versioned windows os. and hms800c compil er only operates under the ms - windows 2000 and up ver sioned windows os. please contact sales part of abov semiconductor. and you can see more information at ( http://www.abov.co.kr ) figure 1 - 1 pgmplususb ( single writer ) figure 1 - 2 sio isp ( in system programmer ) figure 1 - 3 standalone isp (vdd power is not supplied) figure 1 - 4 ez - isp (vdd supplied standalone type isp) figure 1 - 5 standalone gang4 ( for mass production ) figure 1 - 6 standalone gang 8 ( for mass production ) figure 1 - 7 choice - dr ( emulator )
mc81f4 204 10 october 19, 2009 ver. 1.35 1.4 ordering information device name flash rom ram package mc81f4204 r 4k bytes 192 bytes 16_ tssop mc81f4204 m 16 _sop mc81f4204 v 16_ pdip mc81f4204d 20_sop mc81f4204b 20_pdip
mc81f4 204 october 19, 2009 ver. 1.35 11 2. block diagram figure 2 - 1 system block diagram r e s e t p o r t i / o a n d e x t e r r u p t c o n t r o l 4 k x 8 - b i t r o m 8 - b i t t i m e r / c o u n t e r 0 s i o s c k / r 0 4 / a n 2 / e x t 2 / e c 1 8 - b i t t i m e r / c o u n t e r 1 h i g h s p e e d p w m b u z z e r l v r ( p o r ) a / d c o n v e r t e r b a s i c t i m e r / w a t c h d o g t i m e r p o r t 0 g 8 1 0 c p u 1 9 2 x 8 - b i t r a m s i / r 0 5 / a n 3 / e x t 3 / t 1 o / p w m 1 o s o / r 0 6 / a n 4 / e x t 4 / e c 2 a n 0 / r 0 2 / e c 0 / e x t 0 a n 1 / r 0 3 / t 0 o / p w m 0 o / e x t 1 a n 2 / r 0 4 / s c k / e c 1 / e x t 2 a n 3 / r 0 5 / s i / t 1 o / p w m 1 o / e x t 3 a n 4 / r 0 6 / s o / e c 2 / e x t 4 a n 5 / r 0 7 / t 2 o / e x t 5 a n 6 / r 1 1 / p w m 2 o / e x t 7 a n 7 / r 1 2 / p w m 3 o / e x t 8 / b u z o v r e f / r 1 0 / e x t 6 x i n x o u t v d d v s s e x t 0 / a n 0 / r 0 2 / e c 0 a n 1 / r 0 3 / t 0 o / p w m 0 o / e x t 1 e x t 2 / a n 2 / s c k / r 0 4 / e c 1 a n 3 / r 0 5 / t 1 o / p w m 1 o / e x t 3 e x t 7 / a n 6 / r 1 1 / p w m 2 o e x t 8 / b u z o / a n 7 / r 1 2 / p w m 3 o e x t 8 / a n 7 / p w m 3 o / r 1 2 / b u z o r 1 1 / p w m 2 o / e x t 7 / a n 6 r 1 2 / a n 7 / b u z o / p w m 3 o / e x t 8 r 1 3 / a n 8 / e x t 9 r 1 4 e x t 1 0 / r 0 0 e x t 1 1 / r 0 1 p o r t 1 r 3 3 / x o u t r 3 5 / r e s e t b p o r t 3 r 3 1 / a n 1 4 r 3 2 r 3 4 / x i n e c 0 / e x t 0 / a n 0 / r 0 2 p w m 0 o / t 0 o / e x t 1 / a n 1 / r 0 3 e c 1 / e x t 2 / s c k / a n 2 / r 0 4 p w m 1 o / t 1 o / e x t 3 / s i / a n 3 / r 0 5 e c 2 / e x t 4 / s o / a n 4 / r 0 6 t 2 o / e x t 5 / a n 5 / r 0 7 r 1 0 / v r e f / e x t 6 8 - b i t t i m e r / c o u n t e r 2 e x t 4 / a n 4 / s o / r 0 6 / e c 2 a n 5 / r 0 7 / t 2 o / e x t 5 a n 8 / r 1 3 / e x t 9 a n 1 4 / r 3 1
mc81f4 204 12 october 19, 2009 ver. 1.35 3. pin assignmen t 3.1 20 pin - p dip/sop 3.2 16 pin - p di p/sop /tssop e x t 9 / a n 8 / r 1 3 r 1 4 r 3 2 r 3 1 / a n 1 4 1 2 3 4 5 6 7 8 9 1 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 r 0 3 / a n 1 / e x t 1 / t 0 o / p w m 0 o e c 1 / s c k / e x t 2 / a n 2 / r 0 4 p w m 1 o / t 1 o / s i / e x t 3 / a n 3 / r 0 5 e c 2 / s o / e x t 4 / a n 4 / r 0 6 ( s d a t a ) t 2 o / e x t 5 / a n 5 / r 0 7 v d d v r e f / e x t 6 / r 1 0 ( s c l k ) p w m 2 o / e x t 7 / a n 6 / r 1 1 b u z o / p w m 3 o / e x t 8 / a n 7 / r 1 2 r 0 1 / e x t 1 1 r 0 0 / e x t 1 0 v s s r e s e t b / r 3 5 / v p p x i n / r 3 4 x o u t / r 3 3 r 0 2 / a n 0 / e x t 0 / e c 0 m c 8 1 f 4 2 0 4 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 e c 1 / s c k / e x t 2 / a n 2 / r 0 4 p w m 1 o / t 1 o / s i / e x t 3 / a n 3 / r 0 5 e c 2 / s o / e x t 4 / a n 4 / r 0 6 ( s d a t a ) t 2 o / e x t 5 / a n 5 / r 0 7 v d d v r e f / e x t 6 / r 1 0 ( s c l k ) p w m 2 o / e x t 7 / a n 6 / r 1 1 b u z o / p w m 3 o / e x t 8 / a n 7 / r 1 2 r 0 3 / a n 1 / e x t 1 / t 0 o / p w m 0 o r 0 1 / e x t 1 1 r 0 0 / e x t 1 0 v s s r e s e t b / r 3 5 / v p p x i n / r 3 4 x o u t / r 3 3 r 0 2 / a n 0 / e x t 0 / e c 0 m c 8 1 f 4 2 0 4
mc81f4 204 october 19, 2009 ver. 1.35 13 3.3 summary alternative functions pin number pin status at reset 20pin 16pin r00 ext 10 / sxin 17 13 input r01 ext1 1/ sxout 18 14 input r02 an0 / ext 0 /ec0 19 15 input r03 an1 / ext 1 /t0o/pwm0o 20 16 input r04 an2 / ext 2 /ec1/sck 1 1 input r05 an3 / ext 3 /t1o/pwm1o /si 2 2 input r06 an4 / ext 4 /ec2/so 3 3 input r07 an5 / ext 5 /t2o 4 4 input r10 vref/ ext 6 6 6 input r11 an6 / ext 7 /pwm2o 7 7 input r12 an7 / ext 8 /pwm3o/buzo 8 8 input r13 an8 / ext 9 /pwm4o 9 x open - drain out put r14 - 10 x open - drain output r31 an14 11 x open - drain output r32 - 12 x open - drain output r33 xout 13 9 input r34 xin 14 10 input r35 resetb 15 11 input vdd - 5 5 - vss - 16 12 - note : some pins are initialized by open - drain out put mode, when the device is reset. because the pins are hided in 16 pin package and it is stable that hided pins are be in open - drain - output mode.
mc81f4 204 14 october 19, 2009 ver. 1.35 4. package diagram 4.1 20 p dip - mc81f4204b 4.2 20 sop - mc81f4204d
mc81f4 204 october 19, 2009 ver. 1.35 15 4.3 16 p di p - mc81f4204v 4.4 16 sop - mc81f4204m
mc81f4 204 16 october 19, 2009 ver. 1.35 4.5 16 tssop - MC81F4204R
mc81f4 204 october 19, 2009 ver. 1.35 17 5. pin description pin names i/o pin description alternative functions r00 i/o this port is a 1 - bit programmable i/o pin . schmitt trigger input, push - pull , or open - drain output port. when used as an input port, a p ull - up resistor can be specified in 1 - bit . ext 10 r01 ext 11 r02 an0/ec0/ ext 0 r03 an1/t0o/ pwm0o/ ext 1 r04 an2/ec1/sck/ ext 2 r05 an3/si/ ext 3/ t1o/pwm1o r06 an4/ec2/so/ ext 4 r07 an5/t2o/ ext 5 r10 i/o this port is a 1 - bit programmable i/o pin . schmitt trigger input, push - pull , or open - drain output port. when used as an input port, a p ull - up resistor can be specified in 1 - bit . vref/ ext 6 r11 an6/pwm2o/ ext 7 r12 an7/pwm3o/ buzo/ ext 8 r13 an8/ ext 9 r14 C r31 i/o this port is a 1 - bit programmable i/o pin . input, push - pull , or open - drain output port. when used as an input port, a p ull - up resistor can be specified in 1 - bit . an14 r32 C r33 i/o this port is a 1 - bit programmable i/o pin . schmitt trigger input, push - pull , or open - drain output port. when used as an input port, a p ull - up resistor can be specified in 1 - bit . xout r34 xin r35 resetb ext 0 i/o external interrupt input r02/an0/ec0 ext 1 i/o external interrupt input/timer 0 capture input r03/an1/t0o/ pwm0o ext 2 i/o external interrupt input r04/an2/sck/ ec1 ext 3 i/o external interrupt input/timer 1 capture input r05/an3/si/ t1o/pwm1o ext 4 i/o external interrupt input r06/an4/so/ ec2
mc81f4 204 18 october 19, 2009 ver. 1.35 pin names i/o pin description alternative functions ext 5 i/o external interrupt input/timer 2 capture input r07/an5/t2o ext 6 i/o external interrupt input r10/vref ext 7 r11/an6/ pwm2o ext 8 r12/an7/ pwm3o/buzo ext 9 r13/an8 ext 10 r00 ext 11 r01 t0o i/o timer 0 clock output r03/an1/ ext 1/ pwm0o pwm0o i/o pwm 0 clock output r03/an1/ ext 1/ t0o ec0 i/o timer 0 event count input r 02/an0/ ext 0 t1o i/o timer 1 clock output r05/an3/ ext 3/ si/pwm1o pwm1o i/o pwm 1 clock output r05/an3/ ext 3/ si/t1o ec1 i/o timer 1 event count input r04/an2/sck/ ext 2 t2o i/o timer 2 clock output r07/an5/ ext 5 ec2 i/o timer 2 event count input r06/an4/so/ ext 4 pwm2o i/o pwm 2 clock output r11/an6/ ext 7 pwm3o i/o pwm 3 clock output r12/an7/ ext 8/ buzo buzo i/o buzzer signal output r12/an7/ pwm1o/ ext 8 an0 i/o adc input pins r02/ ext 0/ec0 an1 r03/ ext 1/t0o/ pwm0o an2 r04/ ext 2/sck /ec1 an3 r05/ ext 3/si/ t1o/pwm1o an4 r06/ ext 4/so/ ec2 an5 r07/ ext 5/t2o
mc81f4 204 october 19, 2009 ver. 1.35 19 pin names i/o pin description alternative functions an6 i/o adc input pins r11/ ext 7/ pwm2o an7 r12/ ext 8/ pwm3o/buzo an8 r13/ ext 9 an14 r31 sck i/o serial clock input r04/an2/ec1/ ext 2 si i/o serial data input r05/an3/ ext 3/ t1o/pwm1o so i/o serial data output r06/an4/ec2/ ext 4 resetb i system reset pin r35 x in C out C dd C C ss C C ref C
mc81f4 204 20 october 19, 2009 ver. 1.35 6. p ort structure [ schmitt trigger in ] + [ o ut/open - drain - out] + [ xin/xout ] input/output data clock r33 xin r34 xout [ schmitt trigger in ] + [ o ut/open - drain - out] + [s xin/ sx out ] input/output data input data clock r00 ext10 sxin r01 ext11 sxout v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * x i n / x o u t * * i n p u t d a t a * o s c s r o m o p t i o n v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * s x i n / s x o u t * * i n p u t d a t a * o s c s r 0 c o n l
mc81f4 204 october 19, 2009 ver. 1.35 21 [ schmitt trigger in ] + [ o ut / open - drain - out] + [adc] input/output data input data output data adc r02 ext0 / ec0 - an0 r03 ext1 t0o/pwm0o an1 r04 ext2/sck/ec1 sck an2 r05 ext3/si t1o/pwm1o an3 r06 ext4/ec2 so an4 r07 ext5 t2o an5 r10 ext6 - vref r11 ext7 pwm2o an6 r12 ext8 pwm3o/buzo an7 r13 ext9 pwm4o an8 [ schmitt trigger in ] + [ o ut / open - drain - out] input/output data input data output data r14 - - v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * a d c * * i n p u t d a t a * a d c e n a b l e a d c s e l e c t v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * i n p u t d a t a *
mc81f4 204 22 october 19, 2009 ver. 1.35 [ in put] + [ o ut / open - drain - out] + [adc] input/output data input data output data adc r31 - - an14 [i nput] + [out/open - drain out] input/output data r32 v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * a d c * * i n p u t d a t a * a d c e n a b l e a d c s e l e c t v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * i n p u t d a t a *
mc81f4 204 october 19, 2009 ver. 1.35 23 [ schmitt trigger in ] + [open - drain - out] + [reset] r35/resetb d a t a o u t p u t d i s a b l e i / o i n t e r n a l r e s e t l v r e n i n p u t d a t a l v r e n
mc81f4 204 24 october 19, 2009 ver. 1.35 7. electrical characteristics 7.1 absolute maximum ratings parameter symbol ratings unit note supply voltage vdd - 0.3 C +6. 0 v C normal voltage pin vi - 0.3 C vdd+0.3 v voltage on any pin with respect to vss vo - 0.3 C vdd+0.3 v ioh - 10 ma maximum current output sourced by (ioh per i/o pin) ioh - 80 ma maximum current (ioh) iol 15 ma maximum current sunk by (iol per i/o pin) iol 1 2 0 ma maximum current (iol) total power dissipation fxin 600 mw C storage temperature tstg - 65 C +150 c C note : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute max imum rating conditions for extended periods may affect device reliability. 7.2 recommended operating conditions parameter symbol conditions min typ max units operating voltage v dd fx = 1.0 C 4.2mhz 2.2 - 5.5 v fx = 1.0 C 8.0mhz 2.7 - 5.5 fx = 1.0 C 12.0mhz 4.0 - 5.5 operating temperature topr vdd = 2.2 C 5.5v - 40 85 c
mc81f4 204 october 19, 2009 ver. 1.35 25 7.3 a/d converter characteristics ( t a = - 40 ? c to + 85 ? c, v ref = 2. 7 v to 5.5 v ) parameter symbol conditions min typ max units a/d converting resolution C C C 12 C bits integral linearity error ile vref = 5.12v, v ss = 0v, t a = + 25 ? c C C ? lsb differential linearity error dle C C ? offset error of top eot C ? ? offset error of bottom eob C ? ? overall accuracy C C ? ? conversion time t conv C 25 C C ? s analog input voltage vain C v ss C vref v analog reference voltage vref C 2.7 C 5.5 v analog input current i ain vdd = vref = 5v C C 10 ? a analog block current iavdd vdd = vref = 5v C 1 3 ma vdd = vref = 3v C 0.5 1.5 vdd = vref = 5v power down mode C 100 500 na bgr - vdd = 5v, t a = + 25 ? c - 1.67 - v - vdd = 4v, t a = + 25 ? c - 1.63 - v - vdd = 3v, t a = + 25 ? c - 1.62 - v
mc81f4 204 26 october 19, 2009 ver. 1.35 7.4 dc electrical characteristics (t a = - 40 ? c to + 85 ? c, v dd = 2.2 C 5.0 v , vss=0v, f xin =12mhz) parameter symbol conditions min typ max units input high voltage vih1 r0x, r1x, r33 C r35 v dd = 4.5v C 5.5v 0.8vdd C vdd+0.3 v vih2 all input pins except vih1, vih3, v dd = 4.5v C 5.5v 0.7vdd C vdd+0.3 vih3 xin, xout v dd = 4.5v C 5.5v 0.8vdd C vdd+0.3 input low voltage vil1 r0x, r1x, r33 C r35 v dd = 4.5v C 5.5v C 0.3 C 0.2vdd v vil2 all input pins except vih1, vih3, v dd = 4.5v C 5.5v C 0.3 C 0.3vdd vil3 xin, xout v dd = 4.5v C 5.5v C 0.3 C 0.2vdd output high voltage voh all output ports ioh = C 2ma v dd = 4.5v C 5.5v vdd - 1.0 C C v output low voltage vol all output ports iol=15ma v dd = 4.5v C 5.5v C C 2.0 v input high leakage current iih r0x C r3x, vin=vdd C C 1 ua input low leakage current iil r0x C r3x, vin=vss - 1 C C ua pull - up resistor rpu vi=0v, ta=2 5 ? c, r0x C r3x except r35 vdd=5v 25 50 100 k vi=0v, ta=25 ? c, r0x C r3x except r35 vdd=3v 50 100 200
mc81f4 204 october 19, 2009 ver. 1.35 27 7.5 dc electrical characteristics (continued) (t a = - 40 ? c to + 85 ? c, v dd = 2.2 C 5.0 v , vss=0v, f xin =12mhz) parameter symbol conditions min typ max units osc feedback resistor rx xin=vdd, xout=vss ta=25 ? c , vdd=5v 350 700 1500 m supply current idd1 active mode, fx=12mhz, vdd=5v10% crystal oscillator C 8.0 15.0 ma fx=8mhz, vdd=3v10% C 3.0 6.0 isleep1 sleep mode, fx=12mhz, vdd=5v10% crystal oscillator C 2.0 4 .0 ma fx=8mhz, vdd=3v10% C 1.0 2.0 istop stop mode vdd=5.5v, ta=25 ? c C 0.5 5 .0 ua por level 1.82 2.1 v 7.6 input/output capacitance ( t a = - 40 ? c to + 85 ? c, v dd = 0 v ) parameter symbol conditions min typ max units input capacitance cin f=1mhz unmeasured pins are connected vss C C 10 pf output capacitance cout i/o capacitance cio
mc81f4 204 28 october 19, 2009 ver. 1.35 7.7 serial i/o characteristics ( t a = - 40 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v ) parameter symbol conditions min typ max units sck cycle time t kcy external sck source 1,000 C C ns internal sck source 1,000 sck high, low width t kh , t kl external sck source 500 ns internal sck source t kcy /2 C 50 si setup time to sck high t sik external sck source 250 ns internal sck source 250 si hold time to sck high t ksi external sck source 400 ns internal sck source 400 output delay for sck to sout t kso external sck source C C 300 ns internal sck source 250 interrupt input, high,low width t inth , t intl all interrupt, v dd = 5 v 200 C C ns resetb input low width t rsl input, v dd = 5 v 10 C C u s figure 7 - 1 input timing for external interrupts figure 7 - 2 input timing for resetb external interrupt 0.8 v dd 0.2 v dd t inth t inth resetb 0 . 2 v dd t rsl
mc81f4 204 october 19, 2009 ver. 1.35 29 figure 7 - 3 serial interface data transfer timing sck 0.8 v dd 0.2 v dd t inth t inth 0.8 v dd 0.2 v dd t ksi t sik output data si so t kso
mc81f4 204 30 october 19, 2009 ver. 1.35 7.8 data retention voltage in stop mode ( t a = - 40 ? c to + 85 ? c, v dd = 2.2 v to 5.5 v ) parameter symbol conditions min typ max units data retention supply voltage v dddr C 2.2 C 5.5 v data retention supply current i dddr v dddr = 2.2v (t a = 25 ? c), stop mode C C 1 ua figure 7 - 4 stop mode release timing when initiated by an interrupt figure 7 - 5 stop mode release timing when initiated by resetb i d l e m o d e ( w a t c h d o g t i m e r a c t i v e ) v d d n o t e : t w a i t i s t h e s a m e a s 2 5 6 x 1 / b t c l o c k i n t r e q u e s t e x e c u t i o n o f s t o p i n s t r u c t i o n ~ ~ d a t a r e t e n t i o n ~ ~ s t o p m o d e n o r m a l o p e r a t i n g m o d e 0 . 8 v d d t w a i t v d d d r v d d n o t e : t w a i t i s t h e s a m e a s 2 5 6 x 1 0 2 4 x 1 / f x x ( 6 5 . 5 m s @ 4 m h z ) r e s e t b e x e c u t i o n o f s t o p i n s t r u c t i o n ~ ~ d a t a r e t e n t i o n ~ ~ s t o p m o d e o s c i l l a t i o n s t a b i l l i z a t i o n t i m e n o r m a l o p e r a t i n g m o d e t w a i t r e s e t o c c u r s 0 . 2 v d d v d d d r 0 . 8 v d d
mc81f4 204 october 19, 2009 ver. 1.35 31 7.9 lvr (low v o ltage r e set) electrical characteristics ( t a = - 40 ? c to + 85 ? c, v dd = 2.2 v to 5.5 v ) parameter symbol conditions min typ max units lvr voltage vlvr C 2.2 2.4 2.6 v 2.5 2.7 2.9 2.7 3.0 3.3 3.6 4.0 4.4 hysteresis voltage of lvr v C C 10 100 mv current consumption ilvr vdd = 3v C 45 80 ua notes: 1. the c urrent of lvr circuit is consumed when lvr is enabled by rom option . 2. 2 16 /fx ( = 6.55 ms at fx = 10 mhz )
mc81f4x16 32 october 19, 2009 ver. 1.35 7.10 main clock oscillator characteristics (t a = - 4 0 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) oscillator parameter conditions min typ. max units crystal main oscillation frequency 2.2 v C C C C C C C C C C C C C C C C C C figure 7 - 6 crystal/ceramic oscillator figure 7 - 7 external clock c1 c2 x in x out x in x out
mc81f4x16 october 19, 2009 ver. 1.35 3 3 7.11 external rc oscillation characteristics (t a = - 4 0 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) parameter symbol conditions min typ. max units rc oscillator freque - ncy range (1) ferc t a = 25 ? C ? C C C ? ? C C a = 25 ? C C notes: 1. the external resistor is connected between v dd and x in pin and the 270pf capacitor is connected between x in and v ss pin . (x out pin can be used as a normal port). the frequency is adjusted by external resistor. 2. the min/max frequencies are with in the range of rc osc frequency ( 1mhz to 8mhz) 3. data based on characterization results, not tested in production figure 7 - 8 external clock x in r v dd v ss 270pf
mc81f4x16 34 october 19, 2009 ver. 1.35 7.12 in ternal rc oscillation characteristics (t a = - 40 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) parameter symbol conditions min typ. max units rc oscillator frequency (1) firc v dd = 5.5 v, t a = 25 ? C ? ? C ? C C notes: 1. data based on characterization results, not tested in production 2. x in and x out pins can be used as i/o ports. 7.13 main oscillation stabilization time (t a = - 10 ? c to + 70 ? c, v dd = 2. 2 v to 5.5 v) oscillator conditions min typ. max units crystal fx > 1 mhz oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. C C C C C figure 7 - 9 clock timing measurement at xin x in 0 . 8 v dd 0 . 2 v dd t xh t xl 1 / fx
mc81f4x16 october 19, 2009 ver. 1.35 35 7.14 operating voltage range figure 7 - 10 operating voltage range 2 . 2 1 . 0 m h z 4 . 0 5 . 5 . 8 . 0 m h z 1 2 . 0 m h z ( m a i n o s c f r e q u e n c y ) 2 . 7 s u p p l y v o l t a g e ( v ) 4 . 2 m h z
mc81f4x16 36 october 19, 2009 ver. 1.35 7.15 typical characteristics these graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. in some graphs or tables the data presented are outside specified operating range (e.g. outside specified vdd range). this is for information on ly and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distri bution while max or min represents (mean + 3 ) and (mean ? 3 ) respectively where is standard deviation . figure 7 - 11 i dd C v dd in normal mode figure 7 - 12 i sleep C v dd in sleep mode figure 7 - 13 i dd2 C v dd in sub active mode figure 7 - 14 i sleep2 C v dd with sub clock figure 7 - 15 i stop C v dd in stop mode 0 1 2 3 4 5 6 7 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ma 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ma 0 20 40 60 80 100 120 140 160 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ua 0 5 10 15 20 25 30 35 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ua 0.00 0.05 0.10 0.15 0.20 0.25 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ua
mc81f4 204 october 19, 2009 ver. 1.35 37 figure 7 - 16 i oh - v oh at v dd =5v figure 7 - 17 i o l - v o l at v dd =5v - 20 - 18 - 16 - 14 - 12 - 10 - 8 - 6 - 4 - 2 0 2v 2.5v 3v 3.5v 4v 4.5v 4.99v - 40 c 25 c 85 c ma 0 2 4 6 8 10 12 14 16 18 0v 0.23v 0.47v 0.70v - 40 c 25 c 85 c ma
mc81f4 204 38 october 19, 2009 ver. 1.35 figure 7 - 18 v ih1 - v dd figure 7 - 19 v i l 1 - v dd figure 7 - 20 v ih 2 - v dd figure 7 - 21 v i l2 - v dd figure 7 - 22 v ih 3 - v dd figure 7 - 23 v i l3 - v dd 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vih1 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vil1 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vih2 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vil2 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vih3 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vil3
mc81f4 204 october 19, 2009 ver. 1.35 39 figure 7 - 24 8mhz internal osc freq. - v dd figure 7 - 25 ext . r/c osc freq. - v dd at 25 figure 7 - 26 ext . r/c osc freq. - v dd at 85 figure 7 - 27 ext . l r/c osc freq. - v dd at - 40 0 1 2 3 4 5 6 7 8 9 10 2.7v 3.0v 3.3v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz - 40 85 25 0 2 4 6 8 10 12 14 16 18 20 2.2v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz 5.1 ? 12.0 ? 19.7 ? 39.4 ? 61.2 ? 81.0 ? 97.5 ? 122.0 ? 147.2 ? 198.9 ? 339.0 ? 0 2 4 6 8 10 12 14 16 18 20 2.2v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz 5.1 ? 12.0 ? 19.7 ? 39.4 ? 61.2 ? 81.0 ? 97.5 ? 122.0 ? 147.2 ? 198.9 ? 339.0 ? 0 2 4 6 8 10 12 14 16 18 20 2.2v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz 5.1 ? 12.0 ? 19.7 ? 39.4 ? 61.2 ? 81.0 ? 97.5 ? 122.0 ? 147.2 ? 198.9 ? 339.0 ?
mc81f4 204 40 october 19, 2009 ver. 1.35 8. rom option the rom option is a start - condition byte of the chip. the default rom option value is 00 h (lvr en able and external rc is selected ). it can be changed by appropriate writing tools such as pgmplususb, isp , etc. 8.1 r om o ption 7 6 5 4 3 2 1 0 rom option lvren lvrs C C oscs lvren lvr enable/disable bit 0: enable (r35) 1: disable (resetb) lvrs lvr level selection bits 00: 2.4v 01: 2.7v 10: 3.0v 11: 4.0v C bit4 C bit3 not used mc81f 4 204 oscs oscillator selection bits 000: external rc 001: internal rc; 4mhz 010: internal rc; 2mhz 011: internal rc; 1mhz 100: internal rc; 8mhz 101: not available ( note 4 ) 110: not available ( note 5 ) 111: crystal/ceramic oscillator note : 1. when lvr is enabled, lvr level should be set to appropriate value, not default value. 2. when you select the crystal/ceramic oscillator, r33 and r34 pins are automatically selected for xin and xout mode . 3. when you select the external rc, r34 pin is automatically selected for xin mode . 4. if oscs is set by ? 101 ? , oscillator works as ? internal rc; 4mhz ? mode. 5. if oscs is set by ? 110 ? , o s cillator works as ? internal rc; 2mhz ? mode.
mc81f4 204 october 19, 2009 ver. 1.35 41 8.2 read timing rom option is affected 32 mili - second ( typically ) after vdd cross the por level. more precisely saying, the 32 mili - second is the time for 1/2 counting of 1024 divided bit with 4 mhz internal osc. after the rom option is affected, system clock source is changed based on the rom option. and then, rest 1 /2 counting is continued with changed clock source. so, hole stabilization time is variable depend on the clock source. before read rom option after read rom option osc stabilization time formula 250ns x 128(btcr) x 1024( divider ) period x 128(btcr) x 1024( divider ) before + after int - rc 4mhz 32 ms 32 ms 64 ms int - rc 8mhz 32 ms 16 ms 48 ms x - tal 12 mhz 32 ms 10.7 ms 42.7 ms x - ta l 16 mhz 32 ms 8 ms 40 ms note that rom option is affected in osc stabilization time. so even you change the rom option by isp. it is not affected until system is reset. in other words, you must reset the system after change the rom option. table 8 - 1 examples of osc stabilization time por start volt time rom option read 32 ms por level 32 ms @4mhz osc. stabilization time reset process & main program start vdd rising curve figure 8 - 1 rom option read timing diagram
mc81f4 204 42 october 19, 2009 ver. 1.35 9. memory organization this mcu has separate d address spaces for the *p rogram memory * and the *d ata memory * . the program memory is a rom which stores a program code. it is not possible to writ e a data at the p rogram memory while the mcu is running . the data memory is a rem which is used by mcu at running time. 9.1 registers there are few registers which are used for mcu operating. accumulator ( a register ) : accumulator is the 8 - bit general purpose register, which is used for accumulating and some data operation s such as transfer, temporary saving, and conditional j udg ment , etc. and it can be used as a part of 16 - bit register with y register as shown below. x, y registers : in the addressing mode , these are used as a index register . it makes it possible to access at xth or yth memory from specific address. it is extremely effective for referencing a subroutine table and a memory table . figure 9 - 1 configuration of registers figure 9 - 2 configuration of ya 16 - bit registers a a c c u m u l a t o r x x r e g i s t e r y y r e g i s t e r s p s t a c k p o i n t e r p c l p r o g r a m c o u n t e r p c h p s w p r o g r a m s t a t u s w o r d a y a y t w o 8 - b i t r e g i s t e r s c a n b e u s e d a s a y a 1 6 - b i t r e g i s t e r
mc81f4 204 october 19, 2009 ver. 1.35 43 these registers also have increment, decrement, comparison and data transfer functions, and they can be used as a simple accumulator . stack pointer : stack pointer is an 8 - bit register which indicates the current ? push ? point in the stack area. it is used to push and pop when interrupts or general function call is occurre d. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in exce ss of the stack area permitted by the data memory allocating c onfiguration, the user - processed data may be lost. the stack can be located at any position within 0 0h to 0af h of the internal data memory. the sp is not initialized by hardware, requiring to wr ite the initial value (the location with which the use of the stack starts) by using the initialization routine. normally, the initial value of a fh is used. figure 9 - 3 stack pointer figure 9 - 4 stack operation s p 0 0 h s t a c k a d d r e s s ( 0 0 h C 0 a f h ) 1 5 8 7 0 h a r d w a r e f i x e d 0 0 h C 0 a f h p c h p c l p s w 0 0 a f 0 0 a e 0 0 a d 0 0 a c p o p u p a t e x e c u t i o n o f r e t i i n s t r u c t i o n 0 0 a c 0 0 a f p c h p c l p s w 0 0 a f 0 0 a e 0 0 a d 0 0 a c p u s h d o w n a t a c c e p t a n c e o f i n t e r r u p t 0 0 a f 0 0 a c p c h p c l 0 0 a f 0 0 a e 0 0 a d 0 0 a c p o p u p a t e x e c u t i o n o f r e t i n s t r u c t i o n 0 0 a d 0 0 a f p c h p c l 0 0 a f 0 0 a e 0 0 a d 0 0 a c p u s h d o w n a t e x e c u t i o n o f a c a l l / t c a l l / p c a l l 0 0 a f 0 0 a d s p b e f o r e x e c u t i o n s p a f t e r e x c c u t i o n a 0 0 a f 0 0 a e 0 0 a d 0 0 a c p o p u p a t e x e c u t i o n o f p o p i n s t r u c t i o n p o p a ( x , y , p s w ) 0 0 a f 0 0 a e a 0 0 a f 0 0 a e 0 0 a d 0 0 a c p u s h d o w n a t e x e c u t i o n o f p u s h i n s t r u c t i o n p u s h a ( x , y , p s w ) 0 0 a f 0 0 a e s p b e f o r e x e c u t i o n s p a f t e r e x c c u t i o n s t a c k d e p t h 0 0 a f 0 1 0 0
mc81f4 204 44 october 19, 2009 ver. 1.35 program status word : program status word (psw)contains several bits that reflect the current state of the cpu. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithm etic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all interrupts are disabled when cleared to 0. this flag immediately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector address. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00h to 0ffh when this flag is "0". if it is set to "1", addressing area is assigned 100h to 1ffh. it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation invol ving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7fh) or - 128(80h). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] figure 9 - 5 psw ( program status word ) registers n m s b l s b n e g a t i v e f l a g v g b h i z c o v e r f l o w f l a g s e l e c t d i r e c t p a g e b r k f l a g c a r r y f l a g r e c e i v e s c a r r y o u t z e r o f l a g i n t e r r u p t e n a b l e f l a g h a l f c a r r y f l a g r e c e i v e s c a r r y o u t f r o m b i t 1 o f a d d i t i o n o p e r a n d s w h e n g = 1 , p a g e i s s e l e c t e d t o p a g e 1
mc81f4 204 october 19, 2009 ver. 1.35 45 this flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. when the bit instruction is executed, bit 7 of memory is copied to this flag.
mc81f4 204 46 october 19, 2009 ver. 1.35 9.2 p rogram m emory a 16 - bit program counter is capable of addressing up to 64k bytes, but this device has 4 k bytes program memory space only physically i mplemented. accessing a location above ffffh will cause a wrap - around to 0000h. figure 9 - 6 shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffeh and ffffh . as shown in figure 9 - 6 , each area is assigned a fixed location in program memory. program m emory area contains the user program page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall instead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. t he table call service area spaces 2 - byte for every tcall: 0ffc0h for tcall15, 0ffc2h for tcall14, etc., as shown in figure 9 - 7 . the interrupt causes the cpu to jump to specific location where it commences the execution of the service routine. the interrupt service locations spaces 2 - byte interval . the external interrupt 1 , for example , is assigned to location 0fffc h . any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general p urpose program memory. figure 9 - 6 program memory map p c a l l a r e a t c a l l a r e a i n t e r r u p t v e c t o r a r e a 0 f f f f h 0 f f d f h 0 f f e 0 h 0 f f c 0 h 0 f f 0 0 h 0 f e f f h 4 k r o m 0 f 0 0 0 h
mc81f4 204 october 19, 2009 ver. 1.35 47 figure 9 - 7 pcall and tcall memory area 0 f f c 0 h 0 f f c b h p r o g r a m m e m o r y 0 f f c 1 h t c a l l 1 5 t c a l l 1 4 t c a l l 1 3 t c a l l 1 2 t c a l l 1 1 t c a l l 1 0 t c a l l 9 t c a l l 8 t c a l l 7 t c a l l 6 t c a l l 5 t c a l l 4 t c a l l 3 t c a l l 2 t c a l l 1 t c a l l 0 0 f f c 2 h 0 f f c 3 h 0 f f c 4 h 0 f f c 5 h 0 f f c 6 h 0 f f c 7 h 0 f f c 8 h 0 f f c 9 h 0 f f c a h 0 f f c c h 0 f f c d h 0 f f c e h 0 f f c f h 0 f f d 0 h 0 f f d 1 h 0 f f d 2 h 0 f f d 3 h 0 f f d 4 h 0 f f d 5 h 0 f f d 6 h 0 f f d 7 h 0 f f d 8 h 0 f f d 9 h 0 f f d a h 0 f f d b h 0 f f d c h 0 f f d d h 0 f f d e h 0 f f d f h 0 f f 0 0 h p c a l l a r e a m e m o r y p c a l l a r e a ( 2 5 6 b y t e ) 0 f f f f h
mc81f4 204 48 october 19, 2009 ver. 1.35 example : usage of tcall lda #5 tcall 0fh ;1byte instruction : ;instead of 3 bytes : ;normal call ;table call routine func_a : lda lrg0 ret func_b : lda lrg1 ret ;table call add. area org 0ffc0h ;tcall address area dw func_a dw func_b
mc81f4 204 october 19, 2009 ver. 1.35 49 9.3 d ata memory figure 9 - 8 shows the int ernal data memory space availa ble. data memory is divided into three groups, a user ram, stack memory and c ontrol registers . 9.4 user memory the mc8 1 f 4204 has a 192 bytes user memory (ram). ram pages are selected by the rpr register. rpr ram page select register 00 e1 h 7 6 5 4 3 2 1 0 rpr - rpr bit reset value: ---- _ --- 0b r/w r/w r/w r/w r/w r/w r/w r/w r pr bit ram page select bit 0: page 0 1: page 1 note : after setting rpr(ram page select register), be sure to execute setg instruction. whenever clrg instruction is excuted, page0 is selected regardless of rpr. figure 9 - 8 data memory map 0 3 0 0 h 0 0 0 0 h 0 0 a f h p a g e 0 0 0 f f h u s e r m e m o r y o r s t a c k a r e a ( 1 7 6 b y t e s ) c o n t r o l r e g i s t e r ( 8 0 b y t e s ) 0 0 b 0 h ( w h e n g - f l a g = 0 , t h i s p a g e 0 i s s e l e c t e d u s e r m e m o r y ( 1 6 b y t e s ) 0 1 0 f h 0 1 0 0 h p a g e 1
mc81f4 204 50 october 19, 2009 ver. 1.35 9.5 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when retur ning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the program counter and flags. the s ave/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 9 - 4 . . 9.6 control registers ( sfr ) the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer counters, analog to digital converters and i/o ports. the control registers are in address range of 0 b 0 h to 0ff h . it also be called by sfr(special functio n registers). note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. more detailed information of each registers are expl ained in each peripheral section. example : to write at ckctlr ldm ckctlr,#0ah ;divide ratio( 32)
mc81f4 204 october 19, 2009 ver. 1.35 51 address register name mnemonic r/w initial value hex 00b0h timer 0 status and control register t0scr r/w C 0 0 0 0 0 0 0 00b1h timer 0 data register t0dr r/w 1 1 1 1 1 1 1 1 00b2h timer 0 counter register t0cr r 0 0 0 0 0 0 0 0 00b3h timer 1 status and control register t1scr r/w C 0 0 0 0 0 0 0 00b4h timer 1 data register t1dr r/w 1 1 1 1 1 1 1 1 00b5h timer 1 counter register t1cr r 0 0 0 0 0 0 0 0 00b6h timer 2 status and control register t2scr r/w C C 0 0 0 0 0 0 00b7h timer 2 data register t2dr r/w 1 1 1 1 1 1 1 1 00b8h timer 2 counter register t2cr r 0 0 0 0 0 0 0 0 00bdh a/d mode register admr r/w 0 0 0 0 0 0 0 0 00beh a/d converter data register high byte addrh r x x x x x x x x 00bfh a/d converter data register low byte addrl r x x x x C C C C 00c0h r0 port data register r0 r/w 0 0 0 0 0 0 0 0 00c1h r1 port data register r1 r/w C C C 1 1 0 0 0 00c3h r3 port data register r3 r/w C C 0 0 0 1 1 C 00c6h r0 port control register high byte r0conh r/w 0 0 0 0 0 0 C 0 00c7h r0 port control register middle byte r0conm r/w 0 0 0 0 0 0 0 0 00c8h r0 port control register low byte r0conl r/w C C 0 0 0 0 0 0 00c9h r0 port pull - up resistor enable register pur0 r/w 0 0 0 0 0 0 0 0 00cah r0 port external interrupt register high byte eint0h r/w 0 0 0 0 0 0 0 0 00cbh r0 port external interrupt register low byte eint0l r/w 0 0 0 0 0 0 0 0 00cch r0 port external interrupt request register erq0 r/w 0 0 0 0 0 0 0 0 00cdh external interrupt flag register eintf r/w 0 0 0 0 0 0 0 0 00ceh pwm status and control register pwmscr r/w C 0 0 0 C C C C 00cfh pwm period and duty register pwmpdr r/w C C 1 1 1 1 1 1 00d0h pwm2 data register pwm2dr r/w 1 1 1 1 1 1 1 1 00d1h pwm3 data register pwm3dr r/w 1 1 1 1 1 1 1 1 00d3h r1 port control register high byte r1conh r/w C C C C C C 0 1 00d4h r1 port control register middle byte r1conm r/w 0 0 1 0 0 0 C C 00d5h r1 port control register low byte r1conl r/w C C C 0 0 0 0 0 00d6h r1 port pull - up resistor enable register pur1 r/w C C C 0 0 0 0 0 00d7h r1 port external interrupt register eint1 r/w 0 0 0 0 0 0 0 0 00d8h r1 port external interrupt request register erq1 r/w C C C C 0 0 0 0 table 9 - 1 control register 1/4
mc81f4 204 52 october 19, 2009 ver. 1.35 address register name mnemonic r/w initial value hex 00dch r3 port control register high byte r3conh r/w C C 0 0 0 0 0 0 00ddh r3 port control register low byte r3conl r/w 1 0 0 1 1 C C C 00e1h ram page selection register rpr r/w C C C C C C C 0 00e5h buzzer control register buzr r/w 1 1 0 0 C C C C 00e6h buzzer period data register bupdr r/w 1 1 1 1 1 1 1 1 00e7h sio control register siocr r/w C C 0 0 0 0 0 0 00e8h sio data register siodat r/w 0 0 0 0 0 0 0 0 00e9h sio prescaler register siops r/w 0 0 0 0 0 0 0 0 00eah interrupt enable register high byte ienh r/w 0 0 0 0 0 0 C C 00ebh interrupt enable register low byte ienl r/w C 0 C C C 0 C 0 00ech interrupt request register high byte irqh r/w 0 0 0 0 0 0 C C 00edh interrupt request register low byte irql r/w C 0 C C C 0 C 0 00eeh interrupt flag register high byte intfh r/w 0 0 0 0 0 0 C C 00f1h basic timer counter register btcr r x x x x x x x x 00f2h clock control register ckctlr r/w C C C 1 0 1 1 1 00f3h power on reset control register porc r/w 0 0 0 0 0 0 0 0 00f4h watchdog timer register wdtr r/w 0 1 1 1 1 1 1 1 00f5h stop & sleep mode control register sscr r/w 0 0 0 0 0 0 0 0 00f6h watchdog timer status register wdtsr r/w 0 0 0 0 0 0 0 0 00f7h watchdog timer counter register wdtcr r x x x x x x x x table 9 - 2 control register 2/4
mc81f4 204 october 19, 2009 ver. 1.35 53 mnemonic address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex t0scr 00b0h C t0ms t0cc t0cs t0dr 00b1h timer 0 data register t0cr 00b2h timer 0 counter register t1scr 00b3h C t1ms t1c c t1scr t1dr 00b4h timer 1 data register t1cr 00b5h timer 1 counter register t2scr 00b6h C C t2ms t2cc t2scr t2dr 00b7h timer 2 data register t2cr 00b8h timer 2 counter register admr 00bdh ssbit eoc adclk adch addrh 00beh a/d converter data register high byte addrl 00bfh a/d converter data register low byte r0 00c0h r0 port data register r1 00c1h r1 port data register r3 00c3h r3 port data register r0conh 00c6h r07 r06 C r05 r0conm 00c7h r05 r04 r03 r0conl 00c8h C C r02 r01 r00 pur0 00c9h pur07 pur06 pur05 pur04 pur03 pur02 pur01 pur00 eint0h 00cah ext 5ie ext 4ie ext 3ie ext 2ie eint0l 00cbh ext 1ie ext 0ie ext 11ie ext 10ie erq0 00cch ext 5i r ext 4i r ext 3i r ext 2i r ext 1i r ext 0i r ext 11i r ext 10i r eintf 00cdh ext 0 if ext 2 i f ext 4 i f ext 7 i f ext 8 i f ext 9 i f ext 10 i f ext 11 i f pwmscr 00ceh C pol3 pol2 pwms C C C C pwmpdr 00cfh C C p3dh p3dl p2dh p2dl pph ppl pwm2dr 00d0h pwm 2 data register pwm3dr 00d1h pwm 3 data register r1conh 00d3h C C C C C C r14 r1conm 00d4h r13 r12 C C r1conl 00d5h C C C r11 r10 pur1 00d6h C C C pur14 pur13 pur12 pur11 pur10 eint1 00d7h ext 9ie ext 8ie ext 7ie ext 6ie erq1 00d8h C C C C ext 9i r ext 8i r ext 7i r ext 6i r table 9 - 3 control register 3 /4
mc81f4 204 54 october 19, 2009 ver. 1.35 mnemonic address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex r3conh 00d c h C C r35 r34 r33 r3conl 00d d h r32 r31 C C C rpr 00e1h C C C C C C C rpr0 buzr 00e5h buck buss burl C C C C bupdr 00e6h buzzer period data register siocr 00e7h C C csel dat siom siop cclr sedge siodat 00e8h sio data register siops 00e9h sio prescaler register ienh 00eah t0 m ie t0ov i e t1 m ie t1ovi e t2 m ie t2ov i e C C ienl 00ebh C sioie C C C wdtie C btie irqh 00ech t0 m i r t0ovi r t1 m i r t1ovi r t2 m i r t2ovi r C C irql 00edh C sioi r C C C wdti r C bti r intfh 00eeh t0 mi f t0o vi f t1 mi f t1o vi f t2 mi f t2o vi f C C btcr 00f1h basic timer counter register ckctlr 00f2h C C C wdton btcl bts porc 00f3h poren wdtr 00f4h wdtcl wdtcmp sscr 00f5h stop and sleep control register wdtsr 00f6h w atchdog timer status register wdtcr 00f7h watchdog timer counter register table 9 - 4 control register 4/4
mc81f4 204 october 19, 2009 ver. 1.35 55 9.7 addressing modes the mc8 1fxxxx series mcu uses six addressing modes; - register addressing - immediate addressing - direct page addressing - absolute addressing - indexed addressing - indirect addressing register addressing register addressing means to access to the data of the a, x, y, c and psw registers . for example ? asl ( a rithmetic shift left ) ? only accesses the a register. immediate addressing in this mode, second byte (operand) is accessed as a data immediately. example : : adc #35h ;op code is 04 h : : when g - flag is 1, then ram address is defined by 16 - bit address which is composed of 8 - bit ram paging register (rpr) and 8 - bit immediate data. example : : ;when g = 1, rpr = 1 ldm #35h,#55h ;op code is 0 e4 h : :
mc81f4 204 56 october 19, 2009 ver. 1.35 direct page addressing - > dp in this mode, a n address is specified within direct page. current accessed page is selected by rpr(ram p a ge select register). and dp( direct page ) is an one byte data which indicates the target address in the current accessed page. example : : ;when g = 0 lda 35h ;a = [35h] : ; op code is 0c5h : absolute addressing absolute addressing sets corresponding memory data to data, i.e. second byte (operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx,ldy, or, sbc, sta, stx, sty the operation within data memory (ram) : asl, bit, dec, inc, lsr, rol, ror example : : ;when g = 0 adc !0f035h ;a = a + c + rom[0f035h] : ; op code is 07h : example : addressing accesses the address 0135 h regardless of g - flag.
mc81f4 204 october 19, 2009 ver. 1.35 57 : ;when g = 0 inc !0135h ;increase rom[135h] : ; op code is 98h : indexed addressing x indexed direct page (no offset) {x} in this mode, a n address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example : : ;when g = 1, x = 15h lda {x} ;a = rom[(rpr<<8) + x] : ;op code is 0d4h : x indexed direct page, auto increment {x}+ in this mode, a address is specified within direct page by the x register and the content of x is i ncreased by 1. lda, sta
mc81f4 204 58 october 19, 2009 ver. 1.35 example: : ;when g = 0, x = 35h lda {x}+ ;a = rom[(rpr<<8) + x] : ; and x = x + 1 : ;op code is 0dbh : x indexed direct page (8 bit offset) dp+x this address value is the second byte (operand) of command plus the data of x - register. and it assigns the memory in d irect p age. adc, and, cmp, eor, lda, ldy, or, sbc, sta,sty, xma, asl, dec, inc, lsr, rol, ror example : : ;when g = 0, x = 0f 5h lda 45h + x ; op code is 0c6h : ; : ; : y indexed direct page (8 bit offset) dp+y this address value is the second byte (operand) of command plus the data of y - register, which assigns memory in direct page. this is same with above ? x indexed direct page ?. use y register instead of x. y indexed absolute !abs+y accessing the value of 16 - bit absolute address plus y - register value . this addressing mode can specify memory in whole area.
mc81f4 204 october 19, 2009 ver. 1.35 59 example : : ;when y = 55h lda !0fa00h+y ;op code is d5h : indirect addressing direct page indirect [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example : : ;when g = 0 jmp [35h] ;op code is 3fh : x indexed indirect [dp+x] processes memory data as data, assigned by 16 - bit pair memory which i s determined by pair data [dp+x+1][dp+x] operand plus x - register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta
mc81f4 204 60 october 19, 2009 ver. 1.35 example : : ;when g = 0 : ; x = 10h adc [25h + x] ;op code is 16h : y indexed indirect [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16 - bit pair memory paired by operand in direct page plus y - register data. adc, and, cmp, eor, lda, or, sbc, sta example : : ;when g = 0 : ; y = 10h adc [25h + y] ;op code is 17h : absolute indirect [!abs] the program jumps to address specified by 16 - bit absolute address. jmp
mc81f4 204 october 19, 2009 ver. 1.35 61 example : : ;when g = 0 jmp [0e025h] ;op code is 1fh :
mc81f4 204 62 october 19, 2009 ver. 1.35 10. i/o p orts the mc81f 4 204 microcontroller has three i/o ports, p0 ,p1 and p3 . the cpu accesses ports by writing or reading port register directly. the r0 port has following features, - 1 - bit programmable i/o port. - schmitt trigger input, push - pull or open - drain output mode can be selected by software. - a pull - up resistor can be speci fied in 1 - bit. - r00 - r01 can be used as ext 10/sxin, ext 11/sxout - r02 - r07 can be used as ext 0 - ext 5/ad0 - ad5 - r02 - r03 can be used as ec0, t0o/t0pwm - r04 - r05 can be used as ec1/sck, t1o/t1pwm/si - r06 - r07 can be used as ec2/so, t2o the r1 port has following features, - 1 - bit programmable i/o port. - schmitt trigger input, push - pull or open - drain output mode can be selected by software. - a pull - up resistor can be specified in 1 - bit. - r10 - r13 can be used as ext 6 - ext 9/vref, an6 - an8 - r11 - r13 can be used as pwm2o - pwm4o - r12 can be used as buzo the r3 port has following features, - 1 - bit programmable i/o port. - schmitt trigger or normal input, push - pull or open - drain output mode can be selected by software. - r31 can be used as an14 - r 33 - r34 can be used as xout, xin - r35 can be used as resetb
mc81f4 204 october 19, 2009 ver. 1.35 63 10.1 r0 port registers r0conh C r05~07 r0 port control high register 00c6h a reset clears the r0conh register to ? 00h ? , makes r07 - r05 pins input mode. you can use r0conh register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. when programming the port, please remember that any a lternative peripheral i/o function that def i ned by the r0conh register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r0conh r07 r06 C r05 reset value: 0000_00 - 0b r/w r/w r/w r/w r/w r/w C r07 r07/an5/ ext 5/t2o 000: schmitt trigger i nput mode (ext5) 001: output mode, open - drain 010: alternative function (an5) 011: alternative function (t2o) 1xx: o utput mode, p ush - pull r06 r06/an4/ ext 4/so/ec2 000: schmitt trigger i nput mode (ec2 /ext4 ) 001: output mode, open - drain 010: alternative function (an4) 011: alternative function (so) 1xx: o utput mode, p ush - pull C bit1 not used for mc81f 4 204 r05 r05/an3/ ext 3/si/t1o/pwm1o 1: o utput mode, p ush - pull 0: depend on r0conm.7 C ? 1 ? , r05 is push - pull output mode. 2. when r0conh.0 is selected to ? 0 ? , r05 depends on r0conm.7 - .6 bits.
mc81f4 204 64 october 19, 2009 ver. 1.35 r0conm C r03~05 r0 port control middle register 00c7h a reset clears the r0conm register to ? 00h ? , makes r04 - r03 pins input mode. you can use r0conm register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r0conm register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r0conm r05 r04 r03 reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w r05 r05/an3/ ext 3/si/t1o/pwm1o 00: schmitt trigger i nput mode (si /ext3 ) 01: output mode, open - drain 10: alternative function (an3) 11: alternative function (t1o/pwm1o) r04 r04/an2/ ext 2/sck/ec1 000: schmitt trigger i nput mode ( * sck i n / ec1 / ext2 ) 001: output mode, open - drain 010: alternative function (an2) 011: alternative function (sck out) 1xx: o utput mode, p ush - pull r03 r03/an1/ ext 1/t0o/pwm0o 000: schmitt trigger i nput mode (ext1) 001: output mode, open - drain 010: alternative function (an1) 011: alternative function (t0o/pwm0o) 1xx: o utput mode, p ush - pull n o t e : i f y o u w a n t t o use s i o m o d u le i n s l a v e m o d e , y o u m u s t s e t s c k p o r t a s a n i n p u t m ode .
mc81f4 204 october 19, 2009 ver. 1.35 65 r0conl C r00~02 r0 port control low register 00c8h a reset clears the r0conl register to ? 00h ? , makes r02 - r00 pins input mode. you can use r0conl register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r0conl register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r0conl C C r02 r01 r00 reset value: 00h C C C C r02 r02/an0/ ext 0/ec0 00: schmitt trigger i nput mode (ec0 /ext0 ) 01: output mode, open - drain 10: alternative function (an0) 11: o utput mode, p ush - pull r01 r01/sxout/ ext 11 00: schmitt trigger i nput mode (ext11) 01: output mode, open - drain 10: alternative function (sxout) 11: o utput mode, p ush - pull r00 r00/sxin/ ext 10 00: schmitt trigger i nput mode (ext10) 01: output mode, open - drain 10: alternative function (sxin) 11: o utput mode, p ush - pull
mc81f4 204 66 october 19, 2009 ver. 1.35 pur0 r0 port pull - up enable register 00c9h using the pur0 register, you can configure pull - up resistors to individual r 07 - r 00 pins. 7 6 5 4 3 2 1 0 pur0 pur07 pur06 pur05 pur04 pur03 pur02 pur01 pur00 reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w pur07 r07 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur06 r06 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur05 r05 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur04 r04 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur03 r03 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur02 r02 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur01 r01 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur00 r00 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor r0 r0 port data register 00c0h 7 6 5 4 3 2 1 0 r0 r07 r06 r05 r04 r03 r02 r01 r00 reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w in input mode, it represents the r0 port status. in output mode, r0 port represents it. 1: high 0 : low
mc81f4 204 october 19, 2009 ver. 1.35 67 10.2 r1 port registers r1conh C r14 r1 port control high register 00d3h a reset clears the r1conh register to ? ---- _ -- 01b ? , makes the r14 pins to open - drain output mode. you can use r1conh register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r1conh register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r1conh - - - - - - r14 reset value: ---- _ -- 01b r/w r/w r/w r/w r/w r/w r/w r/w C C r14 r14 00: schmitt trigger i nput mode 01: output mode, open - drain 10: not available 11: o utput mode, p ush - pull
mc81f4 204 68 october 19, 2009 ver. 1.35 r1conm C r12~r13 r1 port control middle register 00d4h a reset clears the r1con m register to ? 2 0h ? , makes the r1 3 pin to open - drain output mode and the r1 2 pin to input mode. you can use r1con m register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r1con m register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r1conm r13 r12 C C reset value: 2 0h r/w r/w r/w r/w r/w r/w C C r13 r13/an8/ ext 9/pwm4o 000: schmitt trigger i nput mode (ext9) 001: output mode, open - drain 010: alternative function (an8) 011: alternative function (pwm4o) 1xx: o utput mode, p ush - pull r12 r12/an7/ ext 8/pwm3o/buzo 000: schmitt trigger i nput mode (ext8) 001: output mode, open - drain 010: alternative function (an7) 011: alternative function (pwm3o) 101: alternative function (buzo) 111: o utput mode, p ush - pull o thers: not available C C
mc81f4 204 october 19, 2009 ver. 1.35 69 r1conl C r10~11 r1 port control low register 00d5h a reset clears the r1conl register to ? 00h ? , makes r11 - r10 pins input mode. you can use r1conl register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. when programming the port, please remember that any a lternative peripheral i/o function that def i ned by the r1conl register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r1conl C C C r11 r10 reset value: 00h C C C C C r11 r11/an6/ ext 7/pwm2o 000: schmitt trigger i nput mode (ext7) 001: output mode, open - drain 010: alternative function (an6) 011: alternative function (pwm2o) 1xx: o utput mode, p ush - pull r10 r10/vref/ ext 6 00: schmitt trigger i nput mode (ext6) 01: output mode, open - drain 10: alternative function (vref) 11: o utput mode, p ush - pull
mc81f4 204 70 october 19, 2009 ver. 1.35 pur1 r1 port pull - up enable register 00d6h using the pur 1 register, you can configure pull - up resistors to individual r1 7 - r1 0 pins. 7 6 5 4 3 2 1 0 pur1 - - - pur14 pur13 pur12 pur11 pur10 reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w - bit7 C pur14 r14 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur13 r13 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur12 r12 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur11 r11 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur10 r10 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor r1 r1 port data register 00c1h 7 6 5 4 3 2 1 0 r1 - - - r14 r13 r12 r11 r10 reset value: --- 0_0000b r/w r/w r/w r/w r/w r/w r/w r/w in input mode, it represents the r1 port status. in output mode, r1 port represents it. 1: high 0 : low
mc81f4 204 october 19, 2009 ver. 1.35 71 10.3 r3 port registers r3 conh C r33~r35 r3 port control high register 00dch a reset clears the r3conh register to ? 00h ? , makes r35 - r33 pins input mode. you can use r3conh register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. 7 6 5 4 3 2 1 0 r3conh C C r35 r34 r33 reset value: 00h C C r/w r/w r/w r/w r/w r/w C bit7 C bit6 not used for mc81 f4204 r35 r35/resetb ( *note* ) 00: schmitt trigger i nput mode 01: not available 10: output mode, open - drain 11: not available r34 r34/xin ( *note* ) 00: schmitt trigger i nput mode 01: schmitt trigger i nput pull - up mode 10: output mode, open - drain 11: o utput mode, p ush - pull r33 r33/xout ( *note* ) 00: schmitt trigger i nput mode 01: schmitt trigger i nput pull - up mode 10: output mode, open - drain 11: o utput mode, p ush - pull note : if you want to use resetb, the lvren (rom option [7]) must select to lvr disable mode ( ? 1 ? ). if you want to use r35, the lvren (rom option [7]) must be select ed to lvr enable mode (? 0 ? ). if you want to use x in and x out , the oscs (rom option [2:0]) must select t o crystal/ceramic oscillator mode (111b). if you want to use r33 and r34 , the oscs (rom option [2:0]) must select to internal rc mode ( 001b , 010b, 011b, 100b ). even you are in case of using emulator you must select the rom option switch properly to use th ose r33,r34,r35 ports.
mc81f4 204 72 october 19, 2009 ver. 1.35 r3conl C r3 1 ~r32 r3 port control low register 00d d h a reset clears the r3 conl register to ? 1001_1 --- b ? , makes the r3 2 - r 3 1 pins to open - drain output mode. you can use r 3 conl register setting to select input or output mode (open - drain or push - pull) and enable alternative functions. when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r 3 conl register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r3conl r32 r31 - - - reset value: 1001_1 --- b r/w r/w r/w r/w r/w r/w r/w r/w r32 r32 00: i nput mode 01: i nput pull - up mode 10: output mode, open - drain 11: o utput mode, p ush - pull r31 r31/an14 000: i nput mode 001: i nput pull - up mode 010: alternative function (an14) 011: output mode, open - drain 1xx: o utput mode, p ush - pull - bit2 C r3 r3 port data register 00c3h 7 6 5 4 3 2 1 0 r3 - - r3 5 r3 4 r3 3 r3 2 r3 1 - reset value: -- 00_011 - b r/w r/w r/w r/w r/w r/w r/w r/w in input mode, it represents the r3 port status. in output mode, r3 port represents it. 1: high 0 : low
mc81f4 204 october 19, 2009 ver. 1.35 73 11. interrutp c ontroller the mc8 1 f 4 204 interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit, and master enable flag (i flag of psw). and 2 1 interrupt s ources are provided. the interrupt v ector addresses are shown in ? 11.6 interrupt vector & priority table ? on page 81 . interrupt enable registers are shown in next paragraph . these registers are composed of interrupt enable flags of each interrupt source and these flags determine whether an interrupt w ill be accepted or not. when the enable flag is 0, a corresponding interrupt source is disabled . note that psw contains also a master enable bit, i - flag, which disables all interrupts at once. figure 11 - 1 block diagram of interrupt w a t c h d o g t i m e r i n t e r r u p t t i m e r 0 m a t c h i n t e r r u p t s i o i n t e r r u p t s i o i r s i o i e t 0 m i r t 0 o v i r t 0 o v i e t 0 m i e t i m e r 0 o v e r f l o w i n t e r r u p t t i m e r 1 m a t c h i n t e r r u p t t 1 m i r t 1 o v i r t 1 o v i e t 1 m i e t i m e r 1 o v e r f l o w i n t e r r u p t w d t i r w d t i e p r i o r i t y c o n t r o l r e l e a s e s t o p / s l e e p i - f l a g i n t e r r u p t m a s t e r e n a b l e f l a g t o c p u i n t e r r u p t v e c t o r a d d r e s s g e n e r a t o r b a s i c t i m e r i n t e r r u p t b t i r b t i e t i m e r 2 m a t c h i n t e r r u p t t 2 m i r t 2 o v i r t 2 o v i f t 2 m i e t i m e r 2 o v e r f l o w i n t e r r u p t i n t f h i n t e r r u p t f l a g e x t e r n a l i n t e r r u p t 3 e x t e r n a l i n t e r r u p t 1 e x t 1 i r e x t 3 i r e x t e r n a l i n t e r r u p t 6 e x t e r n a l i n t e r r u p t 5 e x t 5 i r e x t 6 i r e x t 1 i e i n t e r r u p t r e q u e s t i n t e r r u p t e n a b l e e x t 3 i e e x t 5 i e e x t 6 i e e x t e r n a l i n t e r r u p t 2 e x t e r n a l i n t e r r u p t 0 e x t 0 i r e x t 2 i r e x t e r n a l i n t e r r u p t 7 e x t e r n a l i n t e r r u p t 4 e x t 4 i r e x t 7 i r e x t e r n a l i n t e r r u p t 9 e x t e r n a l i n t e r r u p t 8 e x t 8 i r e x t 9 i r e x t 2 i e e x t 0 i e e x t 7 i e e x t 4 i e e x t 9 i e e x t 8 i e e i n t f i n t e r r u p t f l a g e x t e r n a l i n t e r r u p t 1 0 e x t 1 0 i r e x t 1 0 i e e x t e r n a l i n t e r r u p t 1 1 e x t 1 1 i r e x t 1 1 i e
mc81f4 204 74 october 19, 2009 ver. 1.35 11.1 registers ienh interrupt enable high register 00eah 7 6 5 4 3 2 1 0 ienh t0 m ie t0ov i e t1 m ie t1ov i e t2 m ie t2ov i e - - reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w t0 m ie timer 0 match interrupt enable bit 0: disable interrupt 1: enable interrupt t0ov i e timer 0 overflow interrupt enable bit 0: disable interrupt 1: enable interrupt t 1 m ie timer 1 match interrupt enable bit 0: disable interrupt 1: enable interrupt t 1 ov i e timer 1 overflow interrupt enable bit 0: disable interrupt 1: enable interrupt t2 m ie timer 2 match interrupt enable bit 0: disable interrupt 1: enable interrupt t2ov i e timer 2 overflow interrupt enable bit 0: disable interrupt 1: enable interrupt - bit 1 C bit 0 not used for mc81f4204 ienl interrupt enable low register 00ebh 7 6 5 4 3 2 1 0 ienl - sioie - - - wdtie C bitie reset value: 00h r/w r/w r/w r/w r/w r/w C r/w C bit 7 not used for mc81f4204 sioie sio interrupt enable bit 0: disable interrupt 1: enable interrupt C bit5 C bit 3 not used for mc81f4204 wdtie watchdog timer interrupt enable bit 0: disable interrupt 1: enable interrupt C bit1 not used for mc81f4204 btie basic timer interrupt enable bit 0: disable interrupt 1: enable interrupt
mc81f4 204 october 19, 2009 ver. 1.35 75 irqh interrupt requsest high register 00ech 7 6 5 4 3 2 1 0 iqrh t0 m i r t0ovi r t 1 m i r t 1 ovi r t2 m i r t2ovi r - - reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w t0 m i r timer 0 match interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t0ovi r timer 0 overflow interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t 1 m i r timer 1 match interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t 1 ovi r timer 1 overflow interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t2 m i r timer 2 match interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t2ovi r timer 2 overflow interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending - bit 1 C bit 0 not used for mc81f4204 irql interrupt requsest low register 00e d h 7 6 5 4 3 2 1 0 irql - sioi r - - wdti r C bti r reset value: 00h r/w r/w r/w r/w r/w r/w C r/w C bit 7 not used for mc81f4204 sioi r sio interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending C bit5 C bit 3 not used for mc81f4204 wdti r watchdog timer interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending C bit1 not used for mc81 f4204 bti r basic timer interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending
mc81f4 204 76 october 19, 2009 ver. 1.35 intfh interrupt flag high register 00eeh 7 6 5 4 3 2 1 0 intfh t0 mi f t0o vif t1 mi f t1o vi f t2 mi f t2o vi f reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w t0 mi f timer 0 match interrupt flag bit 0: no generation 1: generation t0o vi f timer 0 overflow interrupt flag bit 0: no generation 1: generation t 1 mi f timer 1 match interrupt flag bit 0: no generation 1: generation t 1 o vi f timer 1 overflow interrupt flag bit 0: no generation 1: generation t2 mi f timer 2 match interrupt flag bit 0: no generation 1: generation t2o vi f timer 2 overflow interrupt flag bit 0: no generation 1: generation - bit 1 C bit 0 not used for mc81f4204 note: when you use ? shard interrupt vector ? , those intfh is used to recognize which interrupt is generated . see ? 11.4 shared interrupt vector ? on page 79 for more information. 11.2 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an instruction. interrupt acceptance sequence requires 8 cycles of fxin ( 1 s at fxin= 4mhz) after the completion of the current instruction execution. the interrupt service task is terminated upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i - flag) is clear ed to 0 to temporarily disable the acceptance of any following ma s kable interrupts. when a non - maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the interrupt service program is executed.
mc81f4 204 october 19, 2009 ver. 1.35 77 a interrupt request is not accepted until the i - flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i - flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. saving/restoring general - purpose register the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these registers are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using th e same data memory area for saving registers. the following method is used to save/restore the general - purpose registers. figure 11 - 2 timing chart of inter rupt acceptance and interrupt return instruction figure 11 - 3 saving/restoring in interrupt routine
mc81f4 204 78 october 19, 2009 ver. 1.35 example: register save using push and pop instructions . intxx : push a push x push y ; save acc . ;save x reg. ;save y reg. ;; interrupt processing ;; pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return
mc81f4 204 october 19, 2009 ver. 1.35 79 11.3 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b - flag of psw is set to distinguish b rk from tcall 0. each processing step is determined by b - flag as shown in figure 11.4 shared interrupt vector some interrupts share the interrupt vector address. to recognize which interrupt is occurred, some interrupt flag registers are used. note that, interrupt request bits are cleared after call the interrupt service routine. so interrupt request bits can not be used to recognize which interrupt is occurred . external interrupt group in case of using interrupts of ext group. it is necessary to check the eintf register in the interrupt service routine to find out which external interrupt is occurred. because th e 8 external interrupts share the one interrupt vector address. these flag bits must be cleared by software after reading this register. timer match / overflow in case of using interrupts of timer match and overflow together, it is necessary to check the intfh register in the interrupt service routine to find out which interrupt is occurred. because the timer match and overflow share the on interrupt vector address. see ? intfh ? on page 76 to know which bit is which.
mc81f4 204 80 october 19, 2009 ver. 1.35 11.5 multi interrupt if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the i nterrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. however, multiple processing through software for special features is possible. generally when an interrupt is accepted, t he i - flag is cleared to disable any further interrupt. but as user sets i - flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. in this example, the ext 1 interrupt can be serviced without any pending, even timer1 is in progress. because of re - setting the interrupt enable registers ienh,ienl and master enable ei in figure 11 - 4 execution of multi interrupt
mc81f4 204 october 19, 2009 ver. 1.35 81 11.6 interrupt vector & priority table address interrupt int number priority 0ffe0h basic interval timer int0 15 ( lowest priority) 0ffe2h watchdog timer int1 14 0ffe4h - - 13 0ffe6h timer 2 match/overflow int3 12 0ffe8h timer 1 match/overflow int4 11 0ffeah timer 0 match/overflow int5 10 0ffech - - 9 0ffeeh - - 8 0fff0h sio int8 7 0fff2h - - 6 0fff4h external group int10 5 0fff6h external 6 int11 4 0fff8h external 5 int12 3 0fffah external 3 int13 2 0fffch external 1 int14 1 0fffeh reset int15 0 ( highest priority) note : e xternal interrupt group = ( ext 0, ext 2, ext 4, ext 7 C ext 11) table 11 - 1 interrupt vector & priority
mc81f4 204 82 october 19, 2009 ver. 1.35 12. external i nterrupts the external interrupt pins are edge triggered depending on the ? external interrupt register s ? . the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. 12.1 register s eint0h C ext 2~5 / r04~r07 r0 port external interrupt enable high register 00cah a reset clears the eint0h register to ? 00h ? , disables ext 5 - ext 2 interrupt. you can use eint0h register setting to select disable interrupt or e nable i nterrupt ( by falling, rising, or both falling and rising edge). 7 6 5 4 3 2 1 0 eint0h ext 5ie ext 4ie ext 3ie ext 2ie reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w ext 5ie r07/ ext 5 external interrupt enable bits 00: disable interrupt 01: enable interrupt by falling edge 10: enable interrupt by rising edge 11: enable interrupt by both falling and rising edge ext 4ie r06/ ext 4 external interrupt enable bits ext 3ie r05/ ext 3 external interrupt enable bits ext 2ie r04/ ext 2 external interrupt enable bits
mc81f4 204 october 19, 2009 ver. 1.35 83 eint0l C ext 10,11,0,1 / r00~r03 r0 po rt external interrupt enable low register 00cbh a reset clears the eint0l register to ? 00h ? , disables ext 1 - ext 0, ext 11 - ext 10 interrupt. you can use eint0l register setting to select disable interrupt or e nable i nterrupt ( by falling, rising, or both falling and rising edge). 7 6 5 4 3 2 1 0 eint0l ext 1ie ext 0ie ext 11ie ext 10ie reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w ext 1ie r03/ ext 1 external interrupt enable bits 00: disable interrupt 01: enable interrupt by falling edge 10: enable interrupt by rising edge 11: enable interrupt by both falling and rising edge ext 0ie r02/ ext 0 external interrupt enable bits ext 11ie r01/ ext 11 external interrupt enable bits ext 10ie r00/ ext 10 external interrupt enable bits eint1 C ext 6~9 / r10~r13 r1 port external interrupt enable register 00d7h a reset clears the eint1 register to ? 00h ? , disables ext 9 - ext 6 interrupt. you can use eint1 register setting to select disable interrupt or e nable i nterrupt ( by falling, rising, or both falling and rising edge). 7 6 5 4 3 2 1 0 eint1 ext 9ie ext 8ie ext 7ie ext 6ie reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w ext 9ie r13/ ext 9 external interrupt enable bits 00: disable interrupt 01: enable interrupt by falling edge 10: enable interrupt by rising edge 11: enable interrupt by both falling and rising edge ext 8ie r12/ ext 8 external interrupt enable bits ext 7ie r11/ ext 7 external interrupt enable bits ext 6ie r10/ ext 6 external interrupt enable bits
mc81f4 204 84 october 19, 2009 ver. 1.35 erq0 C ext 10,11,0~5 / r00~r07 r0 port external interrupt request register 00cch when an interrupt is generated, the bit of e rq 0 that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition - activated. 7 6 5 4 3 2 1 0 erq0 ext 5 ir ext 4 ir ext 3 ir ext 2 ir ext 1 ir ext 0 ir ext 11 ir ext 10 ir reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w ext 5 ir r07/ ext 5 external interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending ext 4 ir r06/ ext 4 external interrupt request flag ext 3 ir r05/ ext 3 external interrupt request flag ext 2 ir r04/ ext 2 external interrupt request flag ext 1 ir r03/ ext 1 external interrupt request flag ext 0 ir r02/ ext 0 external interrupt request flag ext 11 ir r01/ ext 11 external interrupt request flag ext 10 ir r00/ ext 10 external interrupt request flag erq1 C ext 6~9 / r10~r13 r1 port external interrupt request register 00d8h when an interrupt is generated, the bit of e rq 1 that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition - activated. 7 6 5 4 3 2 1 0 erq1 C C C C ext 9 ir ext 8 ir ext 7 ir ext 6 ir reset value: 00h C C C C r/w r/w r/w r/w C C ext 9 ir r03/ ext 9 external interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending ext 8 ir r02/ ext 8 external interrupt request flag ext 7 ir r01/ ext 7 external interrupt request flag ext 6 ir r00/ ext 6 external interrupt request flag
mc81f4 204 october 19, 2009 ver. 1.35 85 eintf external interrupt flag register 00cdh 7 6 5 4 3 2 1 0 eintfh ext 0 i f ext 2 i f ext 4 i f ext 7 i f ext 8 i f ext 9 i f ext 10 i f ext 11 i f reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w ext 0 i f ext 0 external interrupt flag 0: no t generat ed 1: generat ed ext 2 i f ext 2 external interrupt flag ext 4 i f ext 4 external interrupt flag ext 7 i f ext 7 external interrupt flag ext 8 i f ext 8 external interrupt flag ext 9 i f ext 9 external interrupt flag ext 10 i f ext 10 external interrupt flag ext 11 i f ext 11 external interrupt flag 12.2 procedure to generate external interrupt, following steps are required, 1. prepare external interrupt sub - routine. 2. s et external interrupt pins to read mode 3. enable the external interrupt and select the edge mode. 4. make sure global interrupt is enabled(use ? ei ? instruction). after finish ab ove steps , the external interrupt sub - routine is calling, when the edge is detected. when the generated external interrupt is one of the external interrupt group, the eintf register is used to recognize which external interrupt is generated.
mc81f4 204 86 october 19, 2009 ver. 1.35 13. o scillation c ircuits there are few example circuits for main oscillators. oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user sh ould consult the crystal manufacturer for appropriate values of external components. 13.1 main oscillation circuit s c1, c2 = 10 ~ 30 pf * the example load capacitor value(c1, c2) is common value but may not be appropriate for some crystal or ceramic resonator. xout pin can be used as a normal pin. figure 13 - 1 crystal/ceramic oscillator figure 13 - 2 external clock figure 13 - 3 external rc oscillator c1 c2 x in x out x in x out
mc81f4 204 october 19, 2009 ver. 1.35 87 xout and xin pins can be used as normal pins 13.2 pcb layout for reference, here is a example layout for oscillator circuit. note : minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wiring to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high current is present. do not fetch signals from the oscillator. figure 13 - 4 internal rc oscillator figure 13 - 5 layout of oscillator pcb circuit
mc81f4 204 88 october 19, 2009 ver. 1.35 14. b asic i nterval t imer the mc8 1f4 204 has one 8 - bit basic interval timer that is free - run and can not be stop ped except when peripheral clock is sto pped . t he basic interval timer generates the time base for watchdog timer counting. it also provides a basic interval timer interrupt (b tif). the 8 - bit basic interval timer register (bt c r) is increased every internal count pulse which is divided by presca ler. since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflow from ffh to 00h, this overflow causes the interrupt to be generated. the basic interval timer is controlled by the clock control register (ckctlr). when wri te "1" to bit btcl of ckctlr, b t c r register is cleared to "0" and restart to count - up. the bit btcl becomes "0" after one machine cycle by hardware. the bit wdton decides watchdog timer or the normal 7 - bit timer. s ource clock can be selected by lower 3 bits of ckctlr.
mc81f4 204 october 19, 2009 ver. 1.35 89 14.1 registers ckctlr clock control reg ister 00f2h 7 6 5 4 3 2 1 0 ckctlr C C C wdton btcl bts reset value: 17h C C C r/w r/w r/w r/w r/w C bit7 C bit5 not used for mc81f 4204 wdton watchdog timer enable bit 0: operate as 7 - bit timer 1: enable watchdog timer btcl basic timer clear bit 0: normal operation (free - run) 1: clear 8 - bit counter (bitr) to 0 , this bit becomes 0 automatically after one machine cycle, and starts counting. bts basic interval timer source clock selection bits 000: fxin/8 001: fxin/16 010: fxin/32 011: fxin/64 100: fxin/128 101: fxin/256 110: fxin/512 111: fxin/1024 ckctlr[2:0] source clock interrupt(overflow) period (ms) @ fxin = 8mhz 000 fxin/8 0.256 001 fxin/16 0.512 010 fxin/32 1.024 011 fxin/64 2.048 100 fxin/128 4.096 101 fxin/256 8.192 110 fxin/512 16.384 111 fxin/1024 32.768 btcr basic timer counter reg ister 00f1h 7 6 5 4 3 2 1 0 btcr o ne byte register reset value: xxh r r r r r r r r a 8 bit count register for the basic interval timer. figure 14 - 1 basic interval timer interrupt period
mc81f4 204 90 october 19, 2009 ver. 1.35 15. watch d og t imer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and resumes the cpu to the normal state. the watchdog timer signal for detecting m alfunction can be selected eit her a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. the watchdog timer use s the b asic i nterval t imer as a clock source. the wa tchdog timer consists of 7 - bit binary counter and the watchdog timer data register. when the value of 7 - bit binary counter is equal to the lower 7 bits of wdtr, the interrupt request flag is generated. this can be used as watchdog timer interrupt or reset the cpu in accordance with the bit wdton. watchdog reset feature is disabled when the watchdog timer status register(wdtsr) value is ? 0a5h ? . note that, wdtsr ? s reset value is ? 00h ? . and reset value of wdton is ? 1 ? . so watchdog timer reset is enabled at re set time. figure 15 - 1 block diagram of basic interval timer/watchdog timer m u x f x x / 1 0 2 4 f x x / 5 1 2 f x x / 2 5 6 f x x / 1 2 8 f x x / 6 4 f x x / 3 2 f x x / 1 6 f x x / 8 p r e s c a l e r f x x s t a r t t h e c p u 8 - b i t u p c o u n t e r b i t r b t c l c l e a r b t i r b t i e b t i n t b c k [ 2 : 0 ] w a t c h d o g c o u n t e r ( 7 - b i t ) 7 - b i t c o m p a r a t o r 7 - b i t c o m p a r e d a t a w d t r w d t c l c l e a r c l e a r w t i r w d t i e w d t i n t o v e r f l o w w d t s r t o r e s e t c p u w d t o n o v e r f l o w b a s i c i n t e r v a l t i m e r i n t r e q u e s t b a s i c i n t e r v a l t i m e r i n t e n a b l e w a t c h d o g t i m e r i n t r e q u e s t w a t c h d o g t i m e r i n t e n a b l e
mc81f4 204 october 19, 2009 ver. 1.35 91 15.1 registers wdtr watchdog timer reg ister 00f4h 7 6 5 4 3 2 1 0 wdtr wdtcl wdtcmp reset value: 7fh r/w r/w r/w r/w r/w r/w r/w r/w wdtcl watchdog timer clear bit 0: free - run count 1: when the wdtcl is set to 1 , binary counter is cleared to 0 . and the wdtcl becomes 0 automatically after one machine cycle. counter count up again. wdtcmp bit6 C bit0 7 - bit compare data wdtsr watchdog timer status reg ister 00f6h 7 6 5 4 3 2 1 0 wdtsr o ne byte register reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w watchdog timer function disable code (for system reset) 10100101: disable watchdog timer function others: enable watchdog timer function figure 15 - 2 watchdog timer timing
mc81f4 204 92 october 19, 2009 ver. 1.35 16. timer 0 /1 the 8 - bit timer 0 /1 are an 8 - bit general - purpose timer. timer 0 /1 ha ve three operating modes, you can select one of them using the appropriate t 0 scr /t1scr setting : - interval timer mode (toggle output at t 0 o /t1o pin) - capture input mode with a rising or falling edge trigger at ext 1/ ext 3 pin - pwm mode (pwm 0o/pwm1o ) 16.1 registers t0dr timer 0 data register 00b1h 7 6 5 4 3 2 1 0 t0dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit compare value register for the timer 0 match interrupt. t0cr timer 0 counter register 00b 2h 7 6 5 4 3 2 1 0 t0cr o ne byte register reset value: 00h r r r r r r r r a 8 - bit count register for the timer 0
mc81f4 204 october 19, 2009 ver. 1.35 93 t0scr timer 0 status and conrol register 00b0h to enable the timer 0 match interrupt, you must set 1 to t0mie(ienh.7). when the timer 0 match interrupt sub - routine is serviced, the timer 0 match interrupt request flag bit, t 0mir(irqh.7), is automatically cleared. to enable the timer 0 overflow interrupt, you must set 1 to t0ovie(ienh.6). when the timer 0 overflow inte rrupt sub - routine is serviced, the timer 0 overflow interrupt request flag bit, t 0ovif(irqh.6), is automatically cleared. 7 6 5 4 3 2 1 0 t0scr t0mod t0ms t0cc t0cs reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w - - not used for mc81f4204 t0ms timer 0 mode selection bit 00: interval mode (t0o) 01: pwm mode (ovf and match interrupt can occur) 1x: capture mode (ovf can occur) t0cc timer 0 counter clear bit 0: no effect 1: clear the timer 0 counter (when write, automatically cleared t0cs timer 0 clock selection bits 0000: counter stop 0001: not available 0010: not available 0011: not available 0100: not available 0101: external clock (ec0) rising edge 0110: external clock (ec0) falling edge 0111: not available 1000: fxx/2 1001: fxx/4 1010: fxx/8 1011: fxx/16 1100: fxx/32 1101: fxx/128 1110: fxx/512 1111: fxx/2048 note : you must set the t0cc(t0scr.4) bit after set t0dr register. the timer 0 counter value is compared with timer 0 buffer register instead of t0dr. and t0dr value is copied to timer 0 buffer register when 1)t0cc is set 2)t0ovir is set 3) t0mir is set.
mc81f4 204 94 october 19, 2009 ver. 1.35 t1dr timer 1 data registe r 00b4h 7 6 5 4 3 2 1 0 t1dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit compare value register for the timer 1 match interrupt. t1cr timer 0 counter register 00b 5h 7 6 5 4 3 2 1 0 t1cr o ne byte register reset value: 00h r r r r r r r r a 8 - bit count register for the timer 1
mc81f4 204 october 19, 2009 ver. 1.35 95 t1scr timer 1 status and control register 00b3h to enable the timer 1 match interrupt, you must set 1 to t1mie. when the timer 1 match interrupt sub - ro utine is serviced, the timer 1 match interrupt request flag bit, t 1mir(irqh.5), is automatically cleared.. to enable the timer 1 overflow interrupt, you must set 1 to t1ovie. when the timer 1 overflow interrupt sub - routine is serviced, the timer 1 overf low interrupt request flag bit, t 1ovir(irqh.4), is automatically cleared. 7 6 5 4 3 2 1 0 t1scr C t1ms t1cc t1cs reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w C bit7 not used for mc81 f4204 t1ms timer 1 mode selection bit 00: interval mode (t1o) 01: pwm mode (ovf and match interrupt can occur) 1x: capture mode (ovf can occur) t1cc timer 1 counter clear bit 0: no effect 1: clear the timer 1 counter (when write, automatically cleared t1cs timer 1 clock selection bits 0000: counter stop 0001: not available 0010: not available 0011: not available 0100: not available 0101: external clock (ec1) rising edge 0110: external clock (ec1) falling edge 0111: not available 1000: fxx/1 1001: fxx/2 1010: fxx/4 1011: fxx/8 1100: fxx/16 1101: fxx/64 1110: fxx/256 1111: fxx/1024 note : you must set the t 1 cc(t 1 scr.4) bit after set t 1 dr register. the timer 1 counter value is compared with timer 1 buffer register instead of t 1 dr. and t 1 dr value is copied to timer 1 buffer .
mc81f4 204 96 october 19, 2009 ver. 1.35 16.2 timer 0 8 - b it mod e timer 0 has the following functional components: - clock frequency divider (fxx divided by 2048, 512, 128, 3 2 , 1 6, 8, 4, 2) with multiplexer - external clock input pin , ec0 ( r02 ) - i/o pins for capture input , ext 1 (r03) or pwm or match output pwm 0o/ t 0 o ( r03 ) - 8 - bit cou nter (t 0 c r ) , 8 - bit comparator, and 8 - bit reference data register (t 0 d r ) - timer 0 status and control register ( t 0scr) - timer 0 overflow interrupt and match interrupt generation figure 16 - 1 8 - bit timer 0 block diagram t 0 o / p w m 0 o t 0 c s t 0 m i r m u x e i n t 0 l e x t 1 t i m e r 0 b u f f e r r e g i s t e r t i m e r 0 d a t a r e g i s t e r 8 - b i t u p c o u n t e r ( r e a d - o n l y ) r 8 d a t a b u s 8 t 0 o v i r t 0 o v i e o v f m a t c h m u x f x x / 1 2 8 e c 0 t 0 o v e r f l o w i n t e r r u p t f x x / 3 2 f x x / 1 6 f x x / 8 f x x / 4 f x x / 2 c o u n t e r s t o p 8 - b i t c o m p a r a t o r t 0 m i e t 0 m a t c h i n t e r r u p t d a t a b u s c l e a r f x x / 5 1 2 e x t 1 i n t e r r u p t c l e a r f x x / 2 0 4 8 t i m e r 0 i n t e n a b l e t i m e r 0 m a t c h i n t r e q u e s t t i m e r 0 o v e r f l o w i n t e n a b l e t i m e r 0 o v e r f l o w i n t r e q u e s t t 0 c r t 0 d r t 0 c c m a t c h s i g n a l t 0 o v f m u x t 0 m s t 0 c c m a t c h s i g n a l t 0 m i f t 0 o v i f
mc81f4 204 october 19, 2009 ver. 1.35 9 7 function description interval timer mode a match signal is generated and t 0 o pins are toggled when the t0cr register value equals the t 0 d r register value . the match signal generates a timer match interrupt and clears the t0cr register . pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (durat ion) of the pulse that is output at the pwm 0o pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t0dr register. in pwm mode, however, the match signal does not clear the counter. inst ead, it runs continuously, overflowing at ff h, and then continues incrementing from 00h. although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in pwm - type applications. instead, the pulse at the pwm 0o pin is held to low level as long as the reference data value is less than or equal to ( ? ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk * 256 . so, the period and duty times are, d uty = t clk * ( t0dr + 1) period = t clk * 256 in order to generate the pwm0o signal, 3 steps are required, steps example c code m ake sure the pwm0o port is set by pwm output mode t0conm = 0x03; s e t the t0dr value properly t0dr = 25; set the t0scr register properly t0scr = 0x38; capture mode in capture mode, you have to set ext1 interrupt. when the ext 1 interrupt is occurred, the t0cr register value is loaded into the t0dr register and the t0cr register is cleared. and the timer 0 overflow interrupt is generated whenever the t0cr value is overflow ed. so, if you count how many overflow is occurred and read the t0dr value in ext1 interrupt routine, it is possible to measure the time between two ext1 interrupts. or it is possible to measure the time from the t0 initial time to the ext1 interrupt occurred time. the time = ( 256 * tclk ) * overflow_count + (tclk * t0dr) note ? t clk ? is the period time of the timer - counter ? s clock source you must set the t0dr value before set the t0scr register. b ecause t0dr value is fetched when the count is started(the t0cc bit is set) or match/overflow event is occurred .
mc81f4 204 98 october 19, 2009 ver. 1.35 16.3 timer 1 8 - bit mode timer 1 has the following functional components: - clock frequency divider (fxx divided by 1024, 256, 64, 16, 8 , 4 , 2, 1) with multiplexer - external clock input pin , ec1 ( r0 4 ) - i/o pins for capture input , ext 3 (r0 5 ) or pwm or match output pwm 1 o/ t 1 o ( r0 5 ) - 8 - bit counter (t 1 c r) , 8 - bit comparator, and 8 - bit reference data register (t 1 d r ) - timer 1 status and control register ( t 1 scr) - timer 1 overflow interrupt and match interrupt generation figure 16 - 2 8 - bit timer 1 block diagram t 1 c s t 1 m i r m u x e i n t 0 l e x t 3 t i m e r 1 b u f f e r r e g i s t e r t i m e r 1 d a t a r e g i s t e r 8 - b i t u p c o u n t e r ( r e a d - o n l y ) r 8 d a t a b u s 8 t 1 o v i r t 1 o v i e o v f m a t c h m u x e c 1 f x x / 4 f x x / 2 f x x / 1 c o u n t e r s t o p 8 - b i t c o m p a r a t o r t 1 m i e d a t a b u s c l e a r f x x / 2 5 6 f x x / 6 4 f x x / 1 6 f x x / 8 c l e a r e x t 3 i n t e r r u p t f x x / 1 0 2 4 t i m e r 1 o v e r f l o w i n t e n a b l e t i m e r 1 o v e r f l o w i n t r e q u e s t t i m e r 1 i n t e n a b l e t i m e r 1 m a t c h i n t r e q u e s t t 1 c r t 1 d r t 1 o / p w m 1 o t 1 c c m a t c h s i g n a l t 1 o v f m u x t 1 m s t 1 c c m a t c h s i g n a l t 1 o v e r f l o w i n t e r r u p t t 1 o v i f t 1 m a t c h i n t e r r u p t t 1 m i f
mc81f4 204 october 19, 2009 ver. 1.35 99 function description interval timer mode a match signal is generated and t 1 o pins are toggled when the t1cr register value equals the t 1 d r register value . the match signal generates a timer match interru pt and clears the t1cr register . pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the pwm 1o pin. as in interval timer mode, a match signal is generated when the counter val ue is identical to the value written to the t1dr register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at ff h, and then continues incrementing from 00h. although you can use the match signa l to generate a timer 1 overflow interrupt, interrupts are not typically used in pwm - type applications. instead, the pulse at the pwm 1 o pin is held to low level as long as the reference data value is less than or equal to ( ? ) the counter value and then t he pulse is held to high level for as long as the data value is greater than ( > ) the counter valu e. one pulse width is equal to tclk * 256 . so, the period and duty times are, d uty = t clk * ( t1dr + 1) period = t clk * 256 in order to generate the pwm1o signal, 3 steps are required, steps example c code m ake sure the pwm1o port is set by pwm output mode t1conm = 0xc0; s e t the t1dr value properly t1dr = 25; set the t1scr register properly t1scr = 0x38; capture mode in capture mode, you have to set ext3 interrupt. when the ext 3 interrupt is occurred, the t1cr register value is loaded into the t1dr register and the t1cr register is cleared. and the timer 1 overflow interrupt is generated whenever the t1cr value is over flow ed. so, if you count how many overflow is occurred and read the t1dr value in ext3 interrupt routine, it is possible to measure the time between two ext3 interrupts. or it is possible to measure the time from the t1 initial time to the ext3 interrupt occurred time. the time = ( 256 * tclk ) * overflow_count + (tclk * t1dr) note ? t clk ? is the period time of the timer - counter ? s clock source you must set the t1dr value before set the t1scr register. b ecause t1dr value is fetched when the count is started(the t1cc bit is set) or match/overflow event is occurred .
mc81f4 204 100 october 19, 2009 ver. 1.35 17. timer 2 the 8 - bit timer 2 is an 8 - bit general - purpose timer. timer 2 ha ve two operating modes, you can select one of them using the appropriate t 2 scr setting : - interva l timer mode (toggle output at t 2 o pin) - capture input mode with a rising or falling edge trigger at ext 5 pin 17.1 registers t2dr timer 2 data register 00b7h 7 6 5 4 3 2 1 0 t2dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit compare value register for the timer 2 match interrupt. t2cr timer 2 counter register 00b8h 7 6 5 4 3 2 1 0 t2cr o ne byte register reset value: 00h r r r r r r r r a 8 - bit count register for the timer 2
mc81f4 204 october 19, 2009 ver. 1.35 101 t2scr timer 2 status and control register ( t2scr ) 00b6h to enable the timer 2 match interrupt, you must set 1 to t2mie. when the timer 2 match interrupt sub - routine is serviced, the timer 1 match inter rupt request flag bit, t 2mir(irqh.3), is automatically cleared. to enable the timer 2 overflow interrupt, you must set 1 to t2ovie. when the timer 2 overflow interrupt sub - routine is serviced, the timer 2 overflow interrupt request flag bit, t 2ovir(irqh.2), is automatically cleared. 7 6 5 4 3 2 1 0 t2scr - C t2ms t2cc t2cs reset value: 00h - C C bit7 - bit6 not used for mc81 f4204 t2ms timer 2 mode selection bit 0: interval mode (t2o) 1: capture mode (ovf can occur) t2cc timer 2 counter clear bit 0: no effect 1: clear the timer 2 counter (when write, automatically cleared t2cs timer 2 clock selection bits 0000: counter stop 0001: not available 0010: not available 0011: not available 0100: not available 0101: external clock (ec2) rising edge 0110: external clock (ec2) falling edge 0111: not available 1000: fxx/1 1001: fxx/2 1010: fxx/4 1011: fxx/8 1100: fxx/16 1101: fxx/64 1110: fxx/256 1111: fxx/1024 note : you must set the t2cc(t2scr.4) bit after set t2dr register. the timer 2 counter value is compared with timer 2 buffer register instead of t2dr. and t2dr value is copied to timer 2 buffer .
mc81f4 204 102 october 19, 2009 ver. 1.35 17.2 timer 2 8 - bit mode timer 2 has the following functional components: - clock frequency divider (fxx divided by 10 24 , 256 , 64 , 1 6 , 8 , 4 , 2 , 1 ) with multiplexer - external clock input pin , ec 2 ( r0 6 ) - i/o pins for capture input , ext 5 (r0 7 ) or match output t 2 o ( r0 7 ) - 8 - bit counter (t 2 c r) , 8 - bit comparator, and 8 - bit reference data register (t 2 d r ) - timer 2 status and control register ( t 2 scr) - timer 2 overflow interrupt and match interrupt generation figure 17 - 1 8 - bit timer 2 block diagram t 2 o t 2 c s t 2 m i r m u x e i n t 0 h e x t 5 t i m e r 2 b u f f e r r e g i s t e r t i m e r 2 d a t a r e g i s t e r 8 - b i t u p c o u n t e r ( r e a d - o n l y ) r 8 d a t a b u s 8 t 2 c c t 2 o v i r t 2 o v i e o v f m a t c h m u x f x x / 6 4 e c 2 f x x / 1 6 f x x / 8 f x x / 4 f x x / 2 f x x / 1 c o u n t e r s t o p 8 - b i t c o m p a r a t o r t 2 m i e d a t a b u s c l e a r m a t c h s i g n a l f x x / 2 5 6 c l e a r e x t 5 i n t e r r u p t f x x / 1 0 2 4 t i m e r 2 o v e r f l o w i n t e n a b l e t i m e r 2 o v e r f l o w i n t r e q u e s t t i m e r 2 i n t e n a b l e t i m e r 2 m a t c h i n t r e q u e s t t 2 c r t 2 d r t 2 o v e r f l o w i n t e r r u p t t 2 o v i f t 2 m a t c h i n t e r r u p t t 2 m i f t 2 c c m a t c h s i g n a l o v e r f l o w s i g n a l
mc81f4 204 october 19, 2009 ver. 1.35 103 function description interval timer mode a match signal is generated and t 2 o pins are toggled when the t2cr register value equals the t 2 d r register value . the match signal generates a timer mat ch interrupt and clears the t2cr register . capture mode in capture mode, you have to set ext 5 interrupt. when the ext 5 interrupt is occurred, the t2cr register value is loaded into the t2dr register and the t2cr register is cleared. and the timer 2 overflow interrupt is generated whenever the t2cr value is overflow ed. so, if you count how many overflow is occurred and read the t2dr value in ext 5 interrupt routine, it is possible to measure the time between two ext 5 interrupts. or it is possible to measure the time from the t2 initial time to the ext 5 interrupt occurred time. the time = ( 256 * tclk ) * overflow_count + (tclk * t2dr) note ? t clk ? is the period time of the timer - counter ? s clock source you must set the t2dr value before set the t2sc r register. b ecause t2dr value is fetched when the count is started(the t2cc bit is set) or match/overflow event is occurred .
mc81f4 204 104 october 19, 2009 ver. 1.35 18. high speed pwm the mc8 1f 4 204 ha s two high speed pwm (pulse width modulation) function which shared with timer 2 . in pwm mode, the r1 1 /pwm 2o, r12/pwm3o, pins operate as a 10 - bit resolution pwm output port. for this mode, the r11 of r1conl and the r12 of r1conm should be set to alternative function mode . the period of the pwm output is determined by the t2dr (t 2 data register) and pwmpdr [ 1 : 0 ] ( pwm period duty register) and the duty of the pwm output is determined by the p wm2 dr , pwm3dr, (pwm d ata regis ter) and pwmpdr [ 5 : 2 ] (pwm period duty register ). user can use pwm data by writing the lower 8 - bit period value to the t 2dr and the higher 2 - bit period value to the pw mpd r[ 1 : 0 ]. and the duty value can be used with the pwm2 dr , pwm3dr, a nd the pwmpdr [ 5 : 2 ] in the same way. figure 18 - 1 high speed pwm block diagram m a t c h 8 - b i t c o m p a r a t o r t i m e r 2 b u f f e r r e g i s t e r t i m e r 2 d a t a r e g i s t e r 2 - b i t 2 - b i t 8 - b i t u p c o u n t e r ( r e a d - o n l y ) r 2 - b i t 2 - b i t 8 - b i t c o m p a r a t o r 2 - b i t m u x f x x / 6 4 e c 2 f x x / 1 6 f x x / 8 f x x / 4 f x x / 2 f x x / 1 c o u n t e r s t o p p w m 2 d a t a r e g i s t e r 2 - b i t p w m 2 b u f f e r r e g i s t e r 2 - b i t t 2 c s p w m 2 o t 2 m i r t 2 m i e t 2 m a t c h i n t e r r u p t t 2 c c c l e a r m a t c h s i g n a l s r q p o l 2 m u x c o u n t e r s t o p n o t e : 1 . w h e n y o u c l e a r e d t h e p o l x a n d c o u n t e r s t o p , p w m x o i s h i g h s t a t u s . 2 . w h e n y o u s e t t h e p o l x a n d c o u n t e r s t o p , p w m x o i s l o w s t a t u s . ( x = 2 , 3 ) 8 - b i t c o m p a r a t o r 2 - b i t p w m 3 d a t a r e g i s t e r 2 - b i t p w m 3 b u f f e r r e g i s t e r 2 - b i t p w m 3 o s r q p o l 3 m u x c o u n t e r s t o p f x x / 2 5 6 f x x / 1 0 2 4 t 2 c r t 2 d r p p h , p p l p 2 d h , p 2 d l p 3 d h , p 3 d l t i m e r 2 m a t c h i n t e n a b l e t i m e r 2 m a t c h i n t r e q u e s t t 2 m i f t 2 c c m a t c h s i g n a l o v e r f l o w s i g n a l
mc81f4 204 october 19, 2009 ver. 1.35 105 the bit pol 2 and pol3 of pwmscr decides the polarity of duty cycle. the duty value can be changed when the pwm outputs. however the changed duty value is output after the current period is over. and it can be maintained the duty value at p resent output when changed only period value shown as example of pwm2 . as it were, the absolute duty time is not changed in varying frequency. note : when user need to change mode from the timer 2 mode to the pwm mode, the timer 2 should be stopped firstly, and then set period and duty register value. if user writes register values and changes mode to pwm mode while timer 2 is in operation, the pwm data would be different from expected data in the beginning. pwm period = [pw mpd r [1 : 0 ]t 2d r+1] x source clock pwm 2 duty = [pw mpd r[ 3 : 2 ]p wm2 dr+1] x source clock pwm 3 duty = [pw mpd r[ 5 : 4 ]p wm3 dr+1] x source clock if it needed more higher frequency of pwm, it should be reduced resolution. note : if the duty value and the period value are same, the pwm output is determined by the bit pol (1: high, 0: low). and if the duty value is set to 00h, the pwm output is determined by the bit pol(1: low, 0: high). the period value must be same or more than the duty value, and 00h cannot be used as the period value. figure 18 - 2 example of pwm2 at 8mhz s o u r c e c l o c k p w m p e r i o d , t 2 d r 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 9 0 a 0 b 0 c 0 d 0 e 0 f 1 0 8 0 8 1 8 2 8 3 8 4 3 f c 3 f d 3 f e 3 f f 0 0 0 1 0 2 0 3 0 4 0 8 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ p w m 2 o , p o l 2 = 1 p w m 2 o , p o l 2 = 0 d u t y c y c l e [ ( 1 + 0 c h ) x 2 5 6 u s = 3 . 3 3 m s t 2 s c r = 1 f h t 2 d r = 0 f f h p w m s c r = 3 0 h p w m p d r = 0 3 h p w m 2 d r = 0 c h p e r i o d c y c l e [ ( 1 + 3 f f h ) x 2 5 6 u s = 2 6 2 m s
mc81f4 204 106 october 19, 2009 ver. 1.35 18.1 registers pwmscr pwm status and control register 00ceh 7 6 5 4 3 2 1 0 pwmscr pol3 pol2 pwms C C C C reset value: 0 - h r/w r/w r/w r/w C C C C - bit 7 not used for mc81f4204 pol3 pwm 3 polarity selection bit 0: pwm 3 duty active low 1: pwm 3 duty active high pol2 pwm 2 polarity selection bit 0: pwm 2 duty active low 1: pwm 2 duty active high pwms pwm selection bit 0: timer 2 mode (interval or capture) 1: pwm mode (pwm2o, pwm3o, pwm4o ) C b i t3 C bit0 not used for mc81f 4204 pwm pdr pwm period duty register 00c f h 7 6 5 4 3 2 1 0 pwmpdr - - p3dh p3dl p2dh p2dl pph ppl reset value: ff h r/w r/w r/w r/w r/w r/w r/w r/w - bit 7 C p3dh pwm 3 duty high bit pwm3 duty value ( 9,8th bits ) p3dl pwm 3 duty low bit p2dh pwm 2 duty high bit pwm2 duty value ( 9,8th bits ) p2dl pwm 2 duty low bit pph pwm period high bit period value ( 9/8th bits ) ppl pwm period low bit
mc81f4 204 october 19, 2009 ver. 1.35 107 pwm2dr pwm 2 data register 00d0h 7 6 5 4 3 2 1 0 pwm2dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit data register for lower bits of 10 - bit pwm 2 duty value. pwm3dr pwm 3 data register 00d 1 h 7 6 5 4 3 2 1 0 pwm3dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit data register for lower bits of 10 - bit pwm 3 duty value.
mc81f4 204 108 october 19, 2009 ver. 1.35 19. buzzer the buzzer driver consists of 8 - bit binary counter, the buzzer period data register bupdr, and the buzzer driver register buzr , the clock selector. it generates square - wave which is very wide rang e frequency ( 244 hz ~ 25 0 k hz at f xx = 8 mhz) by user programmable counter. pin r 12 /buzo is assigned for output port of buzzer driver by setting the bit s r12 of r 1 control middle register (r0 conm ) to 1 01 . the 8 - bit buzzer counter is cleared and start t he counting by writing signal to the register buzr. it is increased from 00 h until it matches with bu pdr [ 7 :0]. also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%. the bit 0 to 7 of bu pd r determines output frequency for buzzer driving. bu pdr is initialized to f f h after reset. frequency calculation is following as shown below. buzzer output freq . = f buz 2 ? ( bupdr + 1 ) figure 19 - 1 buzzer driver block diagram b u z o f / f 8 - b i t c o u n t e r b u c k m u x b u p d r f x x / 1 6 f x x / 3 2 f x x / 6 4 c o m p a r a t o r b u s s b u r l c l e a r m a t c h s i g n a l b u z z e r b u f f e r r e g i s t e r b u r l m a t c h s i g n a l f b u z
mc81f4 204 october 19, 2009 ver. 1.35 109 19.1 registers buzr buzzer driver r egister 00 e5 h 7 6 5 4 3 2 1 0 buzr buck buss burl C C C C reset value: c - h r/w r/w r/w r/w C C C C buck buzzer clock selection bit 00 : not available 01: fxx/16 10: fxx/32 11: fxx/64 buss buzzer start/stop bit 0: disable buzzer 1: enable buzzer burl buzzer data reload bit 0: no effect 1: reload buzzer data to buffer C bit3 C bit1 not used for mc81 f4204 bupdr buzzer period data register 00e6h 7 6 5 4 3 2 1 0 bupdr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit data register for the buzzer period value.
mc81f4 204 110 october 19, 2009 ver. 1.35 19.2 frequency table system clock = 4mhz buck :01 = div16 frequency unit = khz high nibble low nibble of bupdr 0 1 2 3 4 5 6 7 0 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 1 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 2 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 4 1.923 1.894 1.866 1.838 1.812 1.786 1.761 1.736 5 1.543 1.524 1.506 1.488 1.471 1.453 1.437 1.420 6 1.289 1.276 1.263 1.250 1.238 1.225 1.214 1.202 7 1.106 1.096 1.087 1.078 1.068 1.059 1.050 1.042 8 0.969 0.962 0.954 0.947 0.940 0.933 0.926 0.919 9 0.862 0.856 0.850 0.845 0.839 0.833 0.828 0.822 a 0.776 0.772 0.767 0.762 0.758 0.753 0.749 0.744 b 0.706 0.702 0.698 0.694 0.691 0.687 0.683 0.679 c 0.648 0.644 0.641 0.638 0.635 0.631 0.628 0.625 d 0.598 0.595 0.592 0.590 0.587 0.584 0.581 0.579 e 0.556 0.553 0.551 0.548 0.546 0.543 0.541 0.539 f 0.519 0.517 0.514 0.512 0.510 0.508 0.506 0.504 high nibble low nibble of bupdr 8 9 a b c d e f 0 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 1 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 3 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 4 1.712 1.689 1.667 1.645 1.623 1.603 1.582 1.563 5 1.404 1.389 1.374 1.359 1.344 1.330 1.316 1.302 6 1.190 1.179 1.168 1.157 1.147 1.136 1.126 1.116 7 1.033 1.025 1.016 1.008 1.000 0.992 0.984 0.977 8 0.912 0.906 0.899 0.893 0.887 0.880 0.874 0.868 9 0.817 0.812 0.806 0.801 0.796 0.791 0.786 0.781 a 0.740 0.735 0.731 0.727 0.723 0.718 0.714 0.710 b 0.676 0.672 0.668 0.665 0.661 0.658 0.654 0.651 c 0.622 0.619 0.616 0.613 0.610 0.607 0.604 0.601 d 0.576 0.573 0.571 0.568 0.566 0.563 0.561 0.558 e 0.536 0.534 0.532 0.530 0.527 0.525 0.523 0.521 f 0.502 0.500 0.498 0.496 0.494 0.492 0.490 0.488 e x ) bupdr = 0xfc - > freq = 0.494khz
mc81f4 204 october 19, 2009 ver. 1.35 111 20. 12 - bit adc the 12 - bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the 1` input channels to equivalent 12 - bit digital values. the analog input level must lie between the v ref and v ss values. the a/d conver ter has the analog comparator with successive approximation logic, d/a converter logic (resistor string type), a/d mode register (admr), 1 1 multiplexed analog data input pins (ad0 - ad8, ad 14 ,bgr ), and 12 - bit a/d conversion data output register (addrh/addrl). figure 20 - 1 a/d converter block diagram c l o c k s e l e c t o r a d d r h ( r ) , a d d r l ( r ) - + e o c f l a g c o n t r o l l o g i c c o m p a r a t o r a d c h ( s e l e c t o n e i n p u t p i n o f t h e a s s i g n e d p i n s ) a d c l k i n p u t p i n s m u x r e f e r e n c e v o l t a g e v r e f a v s s a n 1 a n 2 a n 7 a n 8 a n 0 a n 1 4 b g r
mc81f4 204 112 october 19, 2009 ver. 1.35 20.1 registers admr a/d mode register 00bdh 7 6 5 4 3 2 1 0 admr ssbit eoc adclk adch reset value: 00h r/w r r/w r/w r/w r/w r/w r/w after reset, the start/stop bit is turned off. you can select only one analog input channel at a time. other analog input (ad0 - ad8, ad14 ,bgr ) can be selected dynamically by manipulating the adch. and the pins not used for analog input can be used for normal i/o f unction. ssbit start or stop bit 0: stop operation 1: start operation eoc end of conversion 0: conversion not complete 1: conversion complete adclk a/d clock selection 00: fxx/1 01: fxx/2 10: fxx/4 11: fxx/8 adch a/d input pin selection 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001: not available 1010: not available 1011: not available 1100: not available 1101: not available 1110: an14 1111: bgr a ddrh a/d converter data high register 00 be h 7 6 5 4 3 2 1 0 addrh .11 .10 .9 .8 .7 .6 .5 .4 reset value: xxh r r r r r r r r a 8 - bit data register for higher 8 - bits of the 12 - bit adc result . addrl a/d converter data low register 00bfh 7 6 5 4 3 2 1 0 addrl .3 .2 .1 .0 - - - - reset value: x - h r r r r r r r r a 8 - bit data register for lower 4 - bits of the 12 - bit adc result.
mc81f4 204 october 19, 2009 ver. 1.35 113 20.2 procedure to do the a/d converting , follow these basic steps: 1. s et the adc pins as the alternative mode. 2. s e t the admr register for - setting adc channel - setting clock - clearing the ? end of conversion ? bit - starting adc 3. w ait until adc is finished ( check the ? end of conversion ? bit ) . when adc is finished, eoc bit is set and ssbit is cleared automatically. 4. read the adcrh and adcrl register . to initiate an analog - to - digital conversion procedure, at first you must set adc pins to alternative function ( ad c analog input ) mode . and you write the channel selection data in the a/d mode register ( a dmr) to select one of analog input channels and set t he conversion start / stop bit, ssbit . the pins not used for adc can be used for normal i/o. to start the a/d conversion, you should set the start / stop bit, ssbit . when a conversion is completed, the end - of - conversion bit , eoc is automatically set to 1 and the result is dumped into the ad dr h/ad dr l register. t hen t he a/d converter enters an idle state. the eoc bit is cleared when ssbit is set. note that, adc interrupt is not provided. note : because the a/d converter has no sample - and - hold circuitry, it is very important that fluctuation of the analog level at the ad0 C ad8, ad 14 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after adc operation is finished. 20.3 c onversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set - up a/d conversion. therefore, total of 66 clocks are required to complete a 12 - bit conversion: when fxx/8 is selected for conversion clock with a 12 mhz fx x clock frequency, one clock cycle is 0.66 ? ? ? ? ? note : the a/d converter needs at least 25 ? ?
mc81f4 204 114 october 19, 2009 ver. 1.35 20.4 i nternal reference v oltage l evels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must be remain ed within the range v ss to v ref . different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 v ref . 20.5 recommended circuit note : 1 . lay out the gnd of v ain as close as possible to the power source. figure 20 - 2 recommended a/d converter circuit v s s m c u a d c i n p u t p o r t a n a l o g i n p u t 1 0 ? f 1 0 4 c 1 0 4 c + - v d d v r e f v d d v a i n ( * n o t e 1 ) 1 0 4 c
mc81f4 204 october 19, 2009 ver. 1.35 115 21. serial i/o interface serial i/o interface modules, si o can interface with various types of external device that require serial data transfer. the components of si o function block are: - 8 - bit control register (si ocr ) - clock selector logic - 8 - bit data register (si o d at ) - 8 - bit pre - scaler register (si o ps) - 3 - bit clock counter - serial data i/o pins (si, so) - serial clock pin (sck) the sio module can transmit or receive 8 - bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select internal or external clock source. figure 21 - 1 sio block diagram s i o i n t 3 - b i t c o u n t e r c l e a r s i o i r f x x / 2 s i o p s s c k c s e l p r e s c a l e r v a l u e = 1 / ( s i o p s + 1 ) s i o i e c l k s i c c l r d a t a b u s s o m u x 1 / 2 8 - b i t p . s . 8 8 - b i t s i o s h i f t b u f f e r ( s i o d a t a ) c l k s e d g e ( e d g e s e l e c t ) s i o m ( m o d e s e l e c t ) s i o p ( s h i f t e n a b l e ) d a t ( l s b / m s b f i r s t m o d e s e l e c t ) s i o i n t r e q u e s t s i o i n t e n a b l e
mc81f4 204 116 october 19, 2009 ver. 1.35 21.1 registers siocr serial i/o interface control register 00e7h a reset clears the si ocr register value to "00h". whit this value, internal clock source and receive - only mode are selected and the 3 - bit counter is cleared . the data shift operation is disabled. the selected data direction is msb - first. 7 6 5 4 3 2 1 0 siocr C C csel dat siom siop cclr sedge reset value: -- 00_0000b C C r/w r/w r/w r/w r/w r/w C bit7 C csel sio shift clock selection bit 0: internal clock ( p.s clock) 1: external clock ( sck) dat data direction control bit 0: msb - first mode 1: lsb - first mode siom sio mode selection bit 0: receive only mode 1: transmit/receive mode siop sio shift operation enable bit 0: disable shifter and clock counter 1: enable shifter and clock counter cclr sio counter clear and shift start bit 0: no action 1: clear 3 - bit counter and start shifting sedge shift clock edge selection bit 0: tx at falling edges, rx at rising edges 1: tx at rising edges, rx at falling edges siodat sio data register 00e8h 7 6 5 4 3 2 1 0 siodat o ne byte register reset value: 00h r /w r/w r/w r/w r/w r/w r/w r/w a 8 - bit data register for sio rx/tx data siops sio pre - scaler register 00e9h 7 6 5 4 3 2 1 0 siops o ne byte register reset value: 00h r /w r/w r/w r/w r/w r/w r/w r/w baud rate = (fxx/4) / (siops+1)
mc81f4 204 october 19, 2009 ver. 1.35 117 21.2 procedure to program the sio module, follow these basic steps: 1. configure the i/o pins at port (sck/si/so) by loading the appropriate value to the r0conm, r0conh register if necessary. - if one side uses a internal clock, the other side must use a external clock. - note that, if the external clock is used, you must set the sck port as an input mode. 2. set siops register with proper pre - scale value. 3 . load an 8 - bit value to the sio cr to properly configure the ser ial i/o module. in this operation, siop [ sioc r. 2 ] bit must be set to "1" to enable the data shifter. 4 . for interrupt generation, set the s io interrupt enable bit , sioie to "1". 5 . data transmit and receiving are occurred at the same time. so before start the shift operation, you must set the siodat with what you want to transmit. - w hen siom [siocr.3] bit is 0, it does not transmit a data. 6. when set sioc r . 1 to 1, the shift operation starts. - with internal clock: sh ift operation is started right after siocr.1 is set. - with external clock: shift operation is started when the master starts the operation . 7. when the shift operation (transmit/receive) is completed, the sio interrupt request flag bit , sioir is set to "1" and sio interrupt request is generated. - don ? t forget to set the siocr.1 bit by 1, to receive next sio data if want. when the sio interrupt sub - routine is serviced, the sio interrupt request flag bit, sioir, is cleared automatically.
mc81f4 204 118 october 19, 2009 ver. 1.35 22. reset 22.1 reset process when the reset even t is occurred , there is a ? stabilization time ? at the beginning. this time is counted from 00h to ffh by bit. so it takes 1/(fxin/ 1024 ) * 256 second. after that, the ? reset process step ? is started. it takes 6 system clock time. a t this time, following status es a re initialized. on - chip hardware initial value p r ogram counter ( pc ) high byte = a byte at ffffh low byte = a byte at f ffeh ffffh and fffeh stores the reset vector. ram page register ( prp ) 0 g - flag ( g ) 0 operation mode oscs setting of rom option control registers initialized by reset values (see ? ? figure 22 - 1 timing diagram after reset 22 - 1 initializing status by reset 1 2 3 4 5 6 7 f f f e f f f f s t a r t f e a d l o p a d h o s c i l l a t o r r e s e t b a d d r e s s b u s d a t a b u s ? s t a b i l i z a t i o n t i m e t s t = f x i n / 1 0 2 4 1 x 2 5 6 r e s e t p r o c e s s s t e p m a i n p r o g r a m
mc81f4 204 october 19, 2009 ver. 1.35 119 22.2 reset sources there are four reset sources in mc81 f4204 . those are external reset, watch dog timer reset, power on reset and low voltage reset. 22.3 external reset when the external reset is enabled and the input signal of reset pin is going to low for a while and going to high, the external reset is occurred .( s ee ? 0 figure 22 - 2 reset sources diagram n o i s e c a n c e l l e r e x t e r n a l r e s e t n o i s e c a n c e l l e r p o r / l v r w d t r e s e t p o w e r o n r e s e t o r l o w v o l t a g e r e s e t b i t c l e a r o v e r f l o w s r q i n t e r n a l r e s e t
mc81f4 204 120 october 19, 2009 ver. 1.35 serial i/o characteristics ? on page 28 for more timing information .) it is possible to use a external power on reset circui t like figure 22 - 3 . 22.4 watch dog timer reset see ? 15 . watch d og t imer ? on page 90 . figure 22 - 3 external power on reset example
mc81f4 204 october 19, 2009 ver. 1.35 121 22.5 power on reset there is a internal power on reset circuit internally. we simply call it por. por o c curs the reset event when vdd is rising over the por level. note that, por can be enabled and disabled by the porc register. and default setting is ? por enable ? . so at the first time power is supplied, por is working always even external reset is enabled. porc power on reset control register (00f3h) 7 6 5 4 3 2 1 0 porc o ne byte register reset value: 00h por enable/disable 01011010: por disable o thers: por enable note : it is recommended to disable the por . when por is enabled, current consumption is increased and, the lvr(low voltage reset) is ignored even the lvr is enabled by the ? rom option ? . 22.6 low voltage reset the low voltage reset occurs the reset event when current vdd is going down under the lvr level. it is configurable by the rom - option. ( see ? 8 . rom option ? on page 40 ) if you want to know more detail timing information , see ? 7.9 lvr (low v o ltage r e set) electrical characteristics ? on page 31 . figure 22 - 4 lvr timing diagram at 4mhz system clock
mc81f4 204 122 october 19, 2009 ver. 1.35 23. power down operation in the power - down mode s , power consumption is reduced considerably. for applications where power consumption is a critical factor, device provides two kinds of power saving functions, stop mode and sleep mode. table 23 - 1 on page 127 shows the status of each power saving mode. sleep mode is entered by the sscr register to 0fh. and stop mode is ent ered by stop instruction after the sscr register to 5ah. 23.1 sleep mode in this mode, the internal oscillation circuits remain active. oscillation continues and peripherals are operate d normally but cpu stops. movement of all peripherals is shown in table 23 - 1 on page 127 . sleep mode is entered by setting the sscr register to 0fh. it is released by reset or interrupt. to be released by interrupt, interrupt should be enabled before sleep mode. sscr stop and sleep control register 00f5h 7 6 5 4 3 2 1 0 sscr o ne byte register reset value: 00h w w w w w w w w it is used to set the stop or sleep mode. 5ah : stop 0fh : sleep note : to get into stop mode, sscr must be set to 5ah just before stop instruction execution. at stop mode, stop & sleep control register (sscr) value is cleared automatically when released. to get into sleep mode, sscr must be set to 0fh . release the sleep mode the exit from sleep mode is hardware reset or all interrupts. reset re - defines all the control registers but does not change the on - chip ram (be careful, if the code is compiled with ram clear option , ram is cleared after reset by ram clear rout ine. it is possible to disable the ram clear option by option menu) . interrupts allow both on - chip ram and control registers to retain their values. if i - flag = 1, the normal interrupt response takes place. if i - flag = 0, the chip will resume execution s tarting with the instruction following the sleep instruction. it will not vector to interrupt service routine. (refer to figure 23 - 3 ) when exit from sleep mode by re set, enough oscillation stabilization time is required to normal operation. figure 23 - 2 shows the timing diagram. when released from the sleep mode, the basic interval timer is activated on wake - up. it is increased from 00 h until ff h . the count overflow is set to start normal op eration.
mc81f4 204 october 19, 2009 ver. 1.35 123 note : after sleep mode, at least one or more nop instruction for data bus pre - charge time should be written. ldm sscr,#0fh nop ;for data bus pre - charge time nop ;for data bus pre - charge t ime figure 23 - 1 sleep mode release timing by external interrupt figure 23 - 2 timing of sleep mode release by reset
mc81f4 204 124 october 19, 2009 ver. 1.35 23.2 stop mode in the stop mode, the main oscillator, system clock and peripheral clock is stopped. with the clock frozen, all functions are stopped, but the on - chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction registers. oscillator stops and the systems internal operations are all held up. the states of the ram, registers, and latches valid immediately before the system is put in the stop state are all held. the program counter stop the address of the instruction to be executed after the instruction "stop" which starts the stop operating mode. note : the stop mode is activated by execution of stop instruction after setting the sscr to 5a h . (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) in the stop mode of operation, v dd can be reduced to minimize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level, before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. note : after stop instruction, at least two or more nop instruction should be written. ex) ldm ckctlr,#0fh ;more than 20ms ldm sscr,#5ah stop nop ;for stabilization time nop ;for stabilization time in the stop operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the p in signal into the high - impedance state, a current flow across the ports input transistor, requiring to fix the level by pull - up or other means.
mc81f4 204 october 19, 2009 ver. 1.35 125 release the stop mode the source for exit from stop mode is hardware reset, external interrupt, timer( ec0, 1 ,2 ), sio . reset re - defines all the control registers but does not change the on - chip ram. if i - flag = 1, the normal interrupt response takes place. if i - flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routine. (refer to figure 23 - 3 ) when exit from stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. figure 23 - 4 shows the timing diagram. when released from the stop mode, the basic interval timer is activated on wake - up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has st arted and stabilized. by reset, exit from stop mode is shown in figure 23 - 5 . figure 23 - 3 stop releasing flow by interrupts
mc81f4 204 126 october 19, 2009 ver. 1.35 before executing stop instruction, basic interval timer must be set properly by software to get stabilization time which is longer than 20ms. figure 23 - 4 st op mode release timing by external interrupt figure 23 - 5 timing of stop mode release by reset
mc81f4 204 october 19, 2009 ver. 1.35 127 23.3 sleep vs stop peripheral stop mode sleep mode cpu stop stop ram retain retain basic interval timer stop operates continuously watchdog timer stop operates continuously timer/counter stop ( t he event counter can operate normally ) operates continuously buzzer, adc stop operates continuously sio only operate d with external clock operates continuously main oscillator stop oscillation i/o ports retain retain control registers retain retain prescale r retain retain address data bus retain retain release source reset, timer( ec 0 / ec 1 / ec 2 ) , sio, external interrupt reset, all interrupts table 23 - 1 peripheral operation during power saving mode
mc81f4 204 128 october 19, 2009 ver. 1.35 23.4 changing the stabilizing time after reset or wake up from the stop/sleep mode, there is a stabilizing time to make sure the system oscillation is stabilized . a ctually the stabilizing time is the basic interval timer ? s one cycle time. so it is adjustable by changing the basic interval timer ? s clock division.( see chapter ? 14 . b asic i nterval t imer ? at page 88 to know how to change the basic interval timer ? s clock division.) it is useful to reduce the power consumption in battery operation with stop/sleep mode. in the battery operation, reducing normal operation time is the key - point to reducing the power consumption. note that, it is not possible after reset. because after reset, the contro l registers are initialized. 23.5 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turnoff output drivers that are sourcing or sinking current, if it is practical . when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption. figure 23 - 6 application example of unused input port
mc81f4 204 october 19, 2009 ver. 1.35 129 in the left case, much current flows from port to gnd. in the left case, tr. base current flows from port to gnd. to avoid power consumption, there should be low output to the port . note : in the stop operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the inp ut level becomes higher than the power voltage level (by approximately 0.3v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the pin signal into the high impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull - up or other means. it should be set properly in order that current flow through port doesn't exist. first consider the port setting to input mode. be sure that there is circuit. in input mode, the pin imped ance viewing from external mcu is very high that the current doesn?t flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if uncertain voltage level (not v ss or v dd ) is applied to input pin, there can be little c urrent (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. the port setting to high or low is decided by considering its relationship with external circuit. for examp le, if there is external pull - up resistor then it is set to output mode, i.e. to high, and if there is external pull - down register, it is set to low. figure 23 - 7 application example of unused output port
mc81f4 204 130 october 19, 2009 ver. 1.35 24. emulator
mc81f4 204 october 19, 2009 ver. 1.35 131 mark name description C C C C C C C C C C C C C C
mc81f4 204 132 october 19, 2009 ver. 1.35 mark name description C ? note : only gnd is connected between eva.board and the target system. vdd is not connected . so, the target system is required it ? s own power source.
mc81f4 204 october 19, 2009 ver. 1.35 133 25. in system programming 25.1 getting started the in - system programming (isp) is an ability to program the code into the mcu while it is installed in a complete system. usb_sio_isp uses both usb to communicate with pc and sio to communicate with mcu. that is why we call it as ? usb_sio_isp ? . in fact there are another isp types. so remember that all mc81f4xxx series use ? usb_sio_isp ? . here is a procedure to use isp. 1. power off the target system. if you use the reset/vpp pin as an output mode, power on timing is very important. so you must read ? entering isp mode at power on time ? and strictly obey the procedure. 2. install the usb_sio_isp software. (it is required a t only first time) 1) download the isp software from http://www.abov.co.kr 2) unzip the downloaded file and connect the usb_sio_isp board. 3) install the driver for usb_sio_isp. (there is a driver file in the zip file .) 3. make sure the hardware condition is satisfied. and connect the isp cable. see ? 25.3 hardware conditions to enter the isp mode ? page 136 , 4. run the software and select a device. all commands are enabled after select the devi ce. 5. power on the target system. if you use the reset/vpp pin as an input mode, power on timing is not that important. but make sure the power is turned - on before execute the isp commands. 6. execute isp commands as you want. if you want to write a code into your mcu, it is recommendable to do following step. ? load file ? - > ? auto ? ( while ? auto option write ? and ? auto show option ? options are enabled ). after finish an isp command is executed, the mcu enters to normal operation mode automatically. so you can see the system is working right after the isp command is finished. ( ? auto ? is assumed as one command ? ) in fact, it is possible to repeat the step - 6 until the hardware condition is changed. b ut in case of reset/vpp pin is used as an output mode, do not repeat step - 6. in that case, you must follow the procedure. see ? entering isp mode at power on time ? for more information . after you change the ? rom option ? , you must do power - off and power - on to reflect the changed ? rom option ? , even you can repeat the step - 6 and see the changed code ? s operation without doing it. the mcu reads the ? rom option ? when only the ? power on reset time ? .
mc81f4 204 134 october 19, 2009 ver. 1.35 25.2 basic isp s/w informa tion the figure 25 - 1 is the usb_sio_ isp software based on ms - windows. this software support s only sio _isp type devices . function description load file load the data from the selected file storage into the memory buffer. save file save the current data in your memory buffer to a disk storage by using the intel motorola hex format. blank check verify whether or not a device is in an erased or un - programmed state. program this button enables you to place new data from the memory buffer into the target device. program write the current data into the mcu. read read the data in the target mcu into the buffer for examination. the checksum will be displayed on the checksum box. figure 25 - 1 isp software
mc81f4 204 october 19, 2009 ver. 1.35 135 verify assures that data in the d evice matches data in the memory buffer. if your device is secured, a verification error is detected. erase erase the data in your target mcu before programming it. option selection set the configuration data of target mcu. the security locking is set with this button. option write progam the configuration data of target mcu. the security locking is performed with this button. auto following sequence is performed ; 1.erase 2.program 3.verify 4.option write auto option write enable the option writing when the ? ? ? ? ? ? ? ? note: mcu configuration value is erased after erase operation. it must be configured to match with user target board. otherwise, it is failed to enter isp mode, or its operation is not desirable.
mc81f4 204 136 october 19, 2009 ver. 1.35 25.3 hardware conditions to enter the isp mode anytime r e s e t/ vpp pin goes +9v , the mcu entering an isp mode except reset/vpp pin is out put mode(see note1). 1. if other signals affect sio communic a tion in isp mode, disconnect these pins by using a jumper or a switch. n ote: 1) u sing reset/vpp pin as an output mode is not recommended even it is possible. anytime reset/vpp pin goes +9v, the mcu entering an isp mode except reset/vpp pin is output mode. if it is output mode, +9v signal is clashing with the output voltage. so if reset/vpp pin is used as an output mode, do not try to execute any isp commands when mcu is in normal operation mode. i t is allowable when only power on time. see ? entering isp mode at power on time ? for more information . 2) there is a 10k ? pull - down register at vpp pin in the isp board. that is why 75k ? register is suggested for r/c reset circuit. so those two register makes a voltage divider circuit when isp b oard is connected. so the vpp level can ? t go down to low level status if the register of reset circuit value is too small. otherwise, if the register value is too large the capacitor value also changed and the reset circuit ? s characteristic s also changed. figure 25 - 2 hardware conditions to enter the isp mode reset/vpp sdata sclk gnd xout vdd xin 7 5 3 1 9 8 6 4 2 1 0 0.1uf 75k ?
mc81f4 204 october 19, 2009 ver. 1.35 137 25.4 entering isp mode at power on time basically anytime +9v signal is forced to reset/vpp pin, the mcu is entering into isp mode. but it makes trouble when the reset/vpp pin is output mode. because the +9v signal is clashing with the port ? s output voltage. but it is possible to enter the isp mode at the power on time even reset/vpp pin is used as an output mode. there is an oscillator stabilizing time when power is turn on. while in the time reset/vpp pin is in input mode even it is used as an output mode in operation time. a proper procedure is required to make sure that isp board catch the oscillator stabilizing time to enter the isp mode. see following procedure. 1. power off the target system. 2. configure the target system as isp mode. 3. a ttach a isp b/d into the target system. 4. run the isp s/w 5. select the target device. 6. power on the target system. 7. execute isp commands as you want. note : power on the target system after select the target device is essential. because when target device is s elected, isp board is getting ready to catch the proper timing to rise the vpp (+9v) signal.
mc81f4 204 138 october 19, 2009 ver. 1.35 25.5 usb - sio - isp board figure 25 - 3 usb - sio - isp board connect usb - mini type cable
mc81f4 204 october 19, 2009 ver. 1.35 139 26. instruction set 26.1 terminology list a accumulator x x - register y y - register psw program status word #imm 8 - bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto - increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000h~0fffh) rel relative addressing data upage u - page (0ff00h~0ffffh) offset address n table call number (0~15) + addition x upper nibble expression in opcode when it is even number (bit7~bit5, bit4=0) y upper nibble expression in opcode when it is odd number (bit7~bit5, bit4=1) ? subtraction ? multiplication ? division ( ) contents expression and or ? exclusive or ~ not assignment / transfer / shift left shift right bit position 1 bit position 0
mc81f4 204 140 october 19, 2009 ver. 1.35 ? exchange = equal not equal 26.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc ? ? ? sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg ? ? ? cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di ? ? ? or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv ? ? ? and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc ? ? ? eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg ? ? ? lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das (n/a) 111 ei ? ? ? ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel ? ? ? sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel ? ? ? cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel ? ? ? or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel ? ? ? and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel ? ? ? eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel ? ? ? lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa (n/a) 111 beq rel ? ? ? sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
mc81f4 204 october 19, 2009 ver. 1.35 141 26.3 instruction set arithmetic / logic no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. a ? ( a ) + ( m ) + c nv -- h - zc 2 adc dp 05 2 3 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 a nd #imm 8 4 2 2 logical and a ? ( a ) ( m ) n - -- - - z - 10 a nd dp 8 5 2 3 11 a nd dp + x 8 6 2 4 12 a nd !abs 8 7 3 4 13 a nd !abs + y 9 5 3 5 14 a nd [ dp + x ] 9 6 2 6 15 a nd [ dp ] + y 9 7 2 6 16 a nd { x } 9 4 1 3 17 asl a 08 1 2 arithmetic shift left n - -- - - z c 18 asl dp 09 2 4 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 4 4 2 2 compare accumulator contents with memory contents ( a ) - ( m ) n - -- - - z c 22 cmp dp 4 5 2 3 23 cmp dp + x 4 6 2 4 24 cmp !abs 4 7 3 4 25 cmp !abs + y 5 5 3 5 26 cmp [ dp + x ] 5 6 2 6 0 c 7 6 5 4 3 2 1 0
mc81f4 204 142 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc 27 cmp [ dp ] + y 5 7 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents ( x ) - ( m ) n - -- - - z c 30 cmpx dp 6c 2 3 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents ( y ) - ( m ) n - -- - - z c 33 cmpy dp 8c 2 3 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1 ? s complement : ( dp ) ? ~( dp ) n - -- - - z - 36 daa - - - unsupported - 37 das - - - unsupported - 38 dec a a8 1 2 decrement m ? ( m ) - 1 n - -- - - z - 39 dec dp a9 2 4 40 dec dp + x b9 2 5 41 dec !abs b8 3 5 42 dec x af 1 2 43 dec y be 1 2 44 div 9b 1 12 divide : ya/x q:a, r:y n v -- h - z - 45 eor #imm a 4 2 2 exclusive or a ? ( a ) ? ( m ) n - -- - - z - 46 eor dp a 5 2 3 47 eor dp + x a 6 2 4 48 eor !abs a 7 3 4 49 eor !abs + y b 5 3 5 50 eor [ dp + x ] b 6 2 6 51 eor [ dp ] + y b 7 2 6 52 eor { x } b 4 1 3 53 inc a 88 1 2 increment m ? ( m ) + 1 n - -- - - z - 54 inc dp 89 2 4
mc81f4 204 october 19, 2009 ver. 1.35 143 no. mnemonic op code byte no cycle no operation flag nvgbhizc 55 inc dp + x 99 2 5 56 inc !abs 98 3 5 57 inc x 8f 1 2 58 inc y 9e 1 2 59 lsr a 48 1 2 arithmetic shift left n - -- - - z c 60 lsr dp 49 2 4 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y ? a n - -- - - z - 64 or #imm 6 4 2 2 logical or a ? ( a ) ( m ) n - -- - - z - 65 or dp 6 5 2 3 66 or dp + x 6 6 2 4 67 or !abs 6 7 3 4 68 or !abs + y 7 5 3 5 69 or [ dp + x ] 7 6 2 6 70 or [ dp ] + y 7 7 2 6 71 or { x } 7 4 1 3 72 rol a 28 1 2 rotate left through carry n - -- - - z c 73 rol dp 29 2 4 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry n - -- - - z c 77 ror dp 69 2 4 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 2 4 2 2 subtract with carry a ? ( a ) - ( m ) - ~( c ) n v - - h z c 81 sbc dp 2 5 2 3 82 sbc dp + x 2 6 2 4 7 6 5 4 3 2 1 0 c c 7 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0 c
mc81f4 204 144 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc 83 sbc !abs 2 7 3 4 84 sbc !abs + y 3 5 3 5 85 sbc [ dp + x ] 3 6 2 6 86 sbc [ dp ] + y 3 7 2 6 87 sbc { x } 3 4 1 3 88 tst dlp 4c 2 3 test memory contents for negative or zero ( dp ) C 00h n - -- - - z - 89 xcn ce 1 5 exchange nibbles within the accumulator a7~a4 ? a3~a0 n - -- - - z -
mc81f4 204 october 19, 2009 ver. 1.35 145 register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c 4 2 2 load accumulator a ? ( m ) n - -- - - z - 2 lda dp c 5 2 3 3 lda dp + x c 6 2 4 4 lda !abs c 7 3 4 5 lda !abs + y d 5 3 5 6 lda [ dp + x ] d 6 2 6 7 lda [ dp ] + y d 7 2 6 8 lda { x } d 4 1 3 9 lda { x } + db 1 4 x - register auto - increment : a ? ( m ) , x ? x + 1 10 ldm dp, #imm e4 3 5 load memory with immediate data : ( m ) ? imm -- -- - - -- 11 ldx #imm 1e 2 2 load x - register x ? ( m ) n - -- - - z - 12 ldx dp cc 2 3 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y - register y ? ( m ) n - -- - - z - 16 ldy dp c9 2 3 17 ldy dp + y d9 2 4 18 ldy !abs d8 3 4 19 sta dp e 5 2 4 store accumulator contents in memory ( m ) ? a -- -- - - -- 20 sta dp + x e 6 2 5 21 sta !abs e 7 3 5 22 sta !abs + y f 5 3 6 23 sta [ dp + x ] f 6 2 7 24 sta [ dp ] + y f 7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x - register auto - increment : ( m ) ? a, x ? x + 1
mc81f4 204 146 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc 27 stx dp ec 2 4 store x - register contents in memory ( m ) ? x -- -- - - -- 28 stx dp + y ed 2 5 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y - register contents in memory ( m ) ? y -- -- - - -- 31 sty dp + x f9 2 5 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x - register : x ? a n - -- - - z - 34 tay 9f 1 2 transfer accumulator contents to y - register : y ? a n - -- - - z - 35 tspx ae 1 2 transfer stack - pointer contents to x - register : x ? sp n - -- - - z - 36 txa c8 1 2 transfer x - register contents to accumulator : a ? x n - -- - - z - 37 txsp 8e 1 2 transfer x - register contents to stack - pointer : sp ? x n - -- - - z - 38 tya bf 1 2 transfer y - register contents to accumulator : a ? y n - -- - - z - 39 xax ee 1 4 exchange x - register contents with accumulator : x ? a -- -- - - -- 40 xay de 1 4 exchange y - register contents with accumulator : y ? a -- -- - - -- 41 xma dp bc 2 5 exchange memory contents with accumulator : ( m ) ? a n - -- - - z - 42 xma dp + x ad 2 6 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x - register contents with y - register : x ? y -- -- - - --
mc81f4 204 october 19, 2009 ver. 1.35 147 16 bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16 - bits add without carry ya ? ( ya ) + ( dp + 1 ) ( dp ) n v -- h - z c 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : ( ya ) - ( dp + 1 ) ( dp ) n - -- - - z c 3 decw dp bd 2 6 decrement memory pair ( dp + 1 ) ( dp ) ? ( dp + 1 ) ( dp ) C 1 n - -- - - z - 4 incw dp 9d 2 6 inc rement memory pair ( dp + 1 ) ( dp ) ? ( dp + 1 ) ( dp ) + 1 n - -- - - z - 5 ldya dp 7d 2 5 load ya ya ? ( dp + 1 ) ( dp ) n - -- - - z - 6 stya dp dd 2 5 store ya ( dp + 1 ) ( dp ) ? ya -- -- - - -- 7 subw dp 3d 2 5 16 - bits subtract without carry ya ? ( ya ) - ( dp + 1 ) ( dp ) n v -- h - z c
mc81f4 204 148 october 19, 2009 ver. 1.35 bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c - flag : c ? ( c ) ( m.bit ) -- -- - - - c 2 and1 b m.bit 8b 3 4 bit and c - flag and not : c ? ( c ) ~( m.bit ) -- -- - - - c 3 bit dp 0c 2 4 bit test a with memory : z ? ( a ) ( m ), n ? ( m7 ), v ? ( m6 ) mm -- - - z - 4 bit !abs 1c 3 5 5 clr 1 dp .bit y1 2 4 clear bit : ( m.bit ) ? 0 -- -- - - -- 6 clra 1 a .bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -- -- - - -- 7 clrc 20 1 2 clear c - flag : c ? 0 -- -- - - - 0 8 clrg 40 1 2 clear g - flag : g ? 0 -- 0 - - - -- 9 clrv 80 1 2 clear v - flag : v ? 0 - 0 - - 0 - -- 10 eor 1 m.bit ab 3 5 bit exclusive - or c - flag : c ? ( c ) ? ( m.bit ) -- -- - - - c 11 eor 1 b m.bit ab 3 5 bit exclusive - or c - flag and not : c ? ( c ) ? ~( m.bit ) -- -- - - - c 12 ldc m.bit cb 3 4 load c - flag : c ? ( m.bit ) -- -- - - - c 13 ldcb m.bit cb 3 4 load c - flag with not : c ? ~( m.bit ) -- -- - - - c 14 not 1 m .bit 4b 3 5 bit complement : ( m.bit ) ? ~( m.bit ) -- -- - - -- 15 or 1 m .bit 6b 3 5 bit or c - flag : c ? c ( m.bit ) -- -- - - - c 16 or 1 b m .bit 6b 3 5 bit or c - flag and not : c ? c ~ ( m.bit ) -- -- - - - c 17 set 1 dp .bit x1 2 4 set bit : ( m.bit ) ? 1 -- -- - - -- 18 seta 1 a .bit 0b 2 2 set a bit : ( a.bit ) ? 1 -- -- - - -- 19 setc a0 1 2 set c - flag : c ? 1 -- -- - - - 1 20 setg c0 1 2 set g - flag : g ? 1 -- 1 - - - -- 21 stc m.bit eb 3 6 store c - flag : ( m.bit ) ? c -- -- - - -- 22 tclr 1 !abs 5c 3 6 test and clear bits with a : a C ( m ), ( m ) ? ( m ) ~( a ) n - -- - - z - 23 tset 1 !abs 3c 3 6 test and set bits with a : a C ( m ), ( m ) ? ( m ) ( a ) n - -- - - z -
mc81f4 204 october 19, 2009 ver. 1.35 149 branch / jump no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a .bit , rel y2 2 4/6 branch if bit clear : if ( bit ) = 0, then pc ? ( pc ) + rel -- -- - - -- 2 bbc dp .bit , rel y3 3 5/7 3 bbs a .bit , rel x2 2 4/6 branch if bit set : if ( bit ) = 1, then pc ? ( pc ) + rel -- -- - - -- 4 bbs dp .bit , rel x3 3 5/7 5 bcc rel 50 2 2/4 branch if carry bit clear : if ( c ) = 0, then pc ? ( pc ) + rel -- -- - - -- 6 bc s rel d0 2 2/4 branch if carry bit set : if ( c ) = 1, then pc ? ( pc ) + rel -- -- - - -- 7 beq rel f0 2 2/4 branch if equal : if ( z ) = 1, then pc ? ( pc ) + rel -- -- - - -- 8 bmi rel 90 2 2/4 branch if minus : if ( n ) = 1, then pc ? ( pc ) + rel -- -- - - -- 9 bne rel 70 2 2/4 branch if not equal : if ( z ) = 0, then pc ? ( pc ) + rel -- -- - - -- 10 bpl rel 10 2 2/4 branch if plus : if ( n ) = 0, then pc ? ( pc ) + rel -- -- - - -- 11 bra rel 2f 2 4 branch always : pc ? ( pc ) + rel -- -- - - -- 12 b v c rel 30 2 2/4 branch if overflow bit clear : if ( v ) = 0, then pc ? ( pc ) + rel -- -- - - -- 13 b vs rel b0 2 2/4 branch if overflow bit set : if ( v ) = 1, then pc ? ( pc ) + rel -- -- - - -- 14 call !abs 3b 3 8 subroutine call m( sp ) ? ( pch ), sp ? sp C 1, m( sp ) ? ( pcl ), sp ? sp C 1, i f !abs, pc ? abs ; if [dp], pcl ? ( dp ), pch ? ( dp + 1 ) -- -- - - -- 15 call [dp] 5f 2 8 16 cbne dp, rel fd 3 5/7 compare and branch if not equal : if ( a ) ( m ), then pc ? ( pc ) + rel -- -- - - -- 17 cbne dp+x , rel 8d 3 6/8 18 d bne dp, rel ac 3 5/7 decrement and branch if not equal : if ( m ) 0, then pc ? ( pc ) + rel -- -- - - -- 19 d bne y , rel 7b 2 4/6 20 jmp !abs 1b 3 3 unconditional jump : pc ? jump address -- -- - - -- 21 jmp [!abs] 1f 3 5 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u - page call m( sp ) ? ( pch ), sp ? sp C 1, -- -- - - --
mc81f4 204 150 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc m( sp ) ? ( pcl ), sp ? sp C 1, pcl ? ( upage ), pch ? 0ffh 24 tcall n na 1 8 table call m( sp ) ? ( pch ), sp ? sp C 1, m( sp ) ? ( pcl ), sp ? sp C 1, pcl ? ( table vector l ), pch ? (table vector h ) -- -- - - -- control operation / etc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt : b ? 1 , m( sp ) ? ( pch ), sp ? sp C 1, m( sp ) ? ( pcl ), sp ? sp C 1, m( sp ) ? ( psw ), sp ? sp C 1, pcl ? ( 0ffdeh ), pch ? ( 0ffdfh ) -- - 1 - 0 -- 2 di 60 1 3 disable interrupt : i ? 0 -- -- - 0 -- 3 ei e0 1 3 enable interrupt : i ? 1 -- -- - 1 -- 4 nop ff 1 2 no operation -- -- ---- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) sp ? sp + 1, x ? m( sp ) sp ? sp + 1, y ? m( sp ) sp ? sp + 1, psw ? m( sp ) -- -- - - -- 6 pop x 2d 1 4 7 pop y 4d 1 4 8 pop psw 6d 1 4 restored 9 push a 0e 1 4 m( sp ) ? a, sp ? sp - 1 m( sp ) ? x, sp ? sp - 1 m( sp ) ? y, sp ? sp - 1 m( sp ) ? psw, sp ? sp - 1 -- -- - - -- 10 push x 2e 1 4 11 push y 4e 1 4 12 push psw 6e 1 4 13 ret 6f 1 5 return from subroutine sp ? sp + 1, pcl ? m( sp ), sp ? sp + 1, pch ? m( sp ) -- -- - - -- 14 reti 7f 1 6 return from interrupt sp ? sp + 1, psw ? m( sp ), sp ? sp + 1, pcl ? m( sp ), sp ? sp + 1, pch ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) -- -- - - --

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